Adding machine driver to instantiate I2S based realtek's ALC5631
sound card on Arndale board.
There are other variants of Audio Daughter Cards for Arndale
Board for which support already exists but there is no support for
Realtek's alc5631 codec hence support for ALC5631 based machine
driver is be
Signed-off-by: Krishna Mohan Dani
---
sound/soc/codecs/Kconfig |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index a68d173..2d85887 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -487,7 +487,8
Signed-off-by: Krishna Mohan Dani
---
sound/soc/codecs/rt5631.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/sound/soc/codecs/rt5631.c b/sound/soc/codecs/rt5631.c
index 1ba27db..d7c3f42 100644
--- a/sound/soc/codecs/rt5631.c
+++ b/sound/soc/codecs/rt5631.c
@@ -1690,6 +1690,1
Document the device tree binding for the ALC5631 codec and update vendor
specific prefix for the Realtek.
Signed-off-by: Krishna Mohan Dani
---
Documentation/devicetree/bindings/sound/rt5631.txt | 41
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devic
These patches add machine driver to instantiate I2S based realtek's
ALC5631 based sound card on Arndale board.
There are other variants of Audio Daughter Cards for Arndale
Board for which support already exists but there is no support for
Realtek's alc5631 codec based card hence support for ALC56
This patch adds new exynos4415.dtsi to support Exynos4415 SoC
based on Cortex-A9 quad cores and includes following dt nodes:
- GIC interrupt controller (GIC-400)
- Pinctrl to control three GPIO parts
- CMU (Clock Management Unit) for CMU/CMU_DMC/AUDSS
- CPU information (Cortex-A9 quad cores)
- UAR
This patchset support new Exynos4415 Samsung SoC based on Cortex-A9 quad cores.
Exynos4415 is a System-On-Chip (SoC) that is based on 32-bit RISC processor
for Smartphone. It is desigend with the 28nm low-power high-K metal gate process
and provides the best performance features.
This patchset inc
This patch add Exynos4415's SoC ID. Exynos4415 is based on the 32-bit RISC
processor for Smartphone. Exynos4415 uses Cortex A9 quad-cores and has a target
speed of 1.6GHz and provides 8.5GB/s memory bandwidth.
Cc: Kukjin Kim
Signed-off-by: Chanwoo Choi
Acked-by: Kyungmin Park
---
arch/arm/mach
From: Tomasz Figa
The pin controllers of Exynos4415 are similar to Exynos4412, but certain
differences cause the need to create separate driver data for it. This
patch adds pin controller and bank descriptor arrays to the driver to
support the new SoC.
Cc: Tomasz Figa
Cc: Thomas Abraham
Cc: Li
This patch adds DT binding documentation for Exynos4415 SoC system
clock controllers.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Kyungmin Park
Signed-off-by: Sylwester Nawrocki
---
.../devicetree/bindings/clock/exynos4415-clock.txt | 38 +
This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9
using common clock framework. The CMU (Clock Management Unit) of Exynos4415
controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses
and function clocks for individual IPs.
Cc: Sylwester Nawrocki
Cc: Tom
This patch adds new clock controller device driver for Exynos4415 SoC.
Changes from v2:
- Fix issue by checkpatch.pl
- Add 'exynos4415' prefix to the name of tables/functions/variables
Changes from v1:
- Separate only clock patches from Exynos4415 patchset[1]
[1] [PATCH 0/5] Support new Exynos44
Hello Mark,
On 10/24/2014 11:02 PM, Mark Brown wrote:
> On Thu, Oct 23, 2014 at 11:28:09AM +0200, Javier Martinez Canillas wrote:
>
> Please fix your mailer to word wrap within paragraphs - you should know
> this by now :/ I've reflowed for legibility.
>
Sorry about that, I was on holidays las
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