FYI your Suggestion was:
You need to add an ifdef around the struct (or perhaps a __maybey_unused
type annotation if there's something suitable) for such configurations.
Following your suggestion I have sent a patch
(187024b36c635bd454c1b1587b58c9439d3a46ad on your git, branch: rt5631 )
Adding machine driver to instantiate I2S based realtek's ALC5631
sound card on Arndale board.
There are other variants of Audio Daughter Cards for Arndale
Board for which support already exists but there is no support for
Realtek's alc5631 codec hence support for ALC5631 based machine
driver is
Kevin Hilman khilman at kernel.org writes:
From: Kevin Hilman khilman at linaro.org
Using the current exynos_defconfig on the exynos5422-odroid-xu3, only
6 of 8 CPUs come online with MCPM boot. CPU0 is an A7, CPUs 1-4 are
A15s and CPU5-7 are the other A7s, but with the current code, CPUs
Fill txstate.residue with the amount of bytes remaining in the current
transfer if the transfer is not complete. This will be of particular
use to i2s DMA transfers, providing more accurate hw_ptr values to ASoC.
I had taken the code from Dylan Reid dgr...@chromium.org patch from the
below link
+CC: Amit Daniel Kachhap
Hi Andrzej,
On Monday 24 November 2014 01:00 PM, Andrzej Hajda wrote:
From: Marek Szyprowski m.szyprow...@samsung.com
This patch adds support for making one power domain a sub-domain of
other domain. This is useful for modeling power dependences for devices
like TV
The divider and mux register offsets and bits are different on
Exynos7 from the older SoCs. Add new pre/post rate change callbacks
for Exynos7 to handle these differences. To do this:
- Add a new exynos_cpuclk_soc_data structure that will hold
the SoC-specific pre/post rate change
Add clock support for the Atlas CPU block in Exynos7.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
.../devicetree/bindings/clock/exynos7-clock.txt|6 +
drivers/clk/samsung/clk-exynos7.c | 121
include/dt-bindings/clock/exynos7-clk.h
These patches add the atlas clocks on Exynos7. It also modifies the
existing cpu clock infrastructure to handle exynos7 differences. These
patches are a pre-requisite for enabling CPUFreq on Exynos7.
Following are the dependencies:
1) arch: arm64: Enable support for Samsung Exynos7 SoC
In case of SoCs with multiple CMUs like Exynos7 and Exynos5260 we are
making use of a common samsung_cmu_register_one function for pll, div,
mux registration. To register the cpu domain clock (for cpufreq) we need
a reference to this clock provider information in the cpu cmu block. Make
this
Add the Atlas CPU clock configuration data and instantiate the CPU clock
type for Exynos7.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
drivers/clk/samsung/clk-cpu.h |5 +
drivers/clk/samsung/clk-exynos7.c | 28 +++-
On 2014년 11월 25일 23:02, Ajay kumar wrote:
On Tue, Nov 25, 2014 at 6:59 PM, Inki Dae inki@samsung.com wrote:
On 2014년 11월 25일 22:08, Ajay kumar wrote:
Hi Inki,
On Tue, Nov 25, 2014 at 6:30 PM, Inki Dae inki@samsung.com wrote:
On 2014년 11월 25일 21:17, Ajay kumar wrote:
ping.
You'd
This patch series adds regulator-haptic driver.
The regulator-haptic has haptic motor and it is controlled by
voltage of regulator via force feedback framework.
Changes in v3:
- fix typo in Documentation
- add define in header file
Changes in v2:
- remove driver owner
- merge
Hi Vivek,
On Mon, Nov 24, 2014 at 6:36 PM, Vivek Gautam gautam.vi...@samsung.com wrote:
BUS1 pinctrl provides gpios for usb and power regulator
available on exynos7-espresso board. So add relevant device
node for pinctrl-bus1.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
This patch adds regulator-haptic device node controlled by regulator.
Signed-off-by: Jaewon Kim jaewon02@samsung.com
Reviewed-by: Chanwoo Choi cw00.c...@samsung.com
---
arch/arm/boot/dts/exynos3250-rinato.dts |7 +++
1 file changed, 7 insertions(+)
diff --git
This patch adds support for haptic driver controlled by
voltage of regulator. And this driver support for
Force Feedback interface from input framework
Signed-off-by: Jaewon Kim jaewon02@samsung.com
Signed-off-by: Hyunhee Kim hyunhee@samsung.com
Acked-by: Kyungmin Park
Hi Vivek,
On Mon, Nov 24, 2014 at 6:32 PM, Vivek Gautam gautam.vi...@samsung.com wrote:
USB and Power regulator on Exynos7 require gpios available
in BUS1 pin controller block.
So adding the BUS1 pinctrl support.
Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com
Signed-off-by:
The audio subsystem on Exynos 5420 has separate clocks and GPIO. To
operate properly on GPIOs the main block clock 'mau_epll' must be
enabled.
This was observed on Peach Pi/Pit and Arndale Octa (after enabling i2s0)
after introducing runtime PM to pl330 DMA driver. After that commit the
During driver unbind the syscore ops were not unregistered which lead to
double add on syscore list:
$ echo 381.audss-clock-controller
/sys/bus/platform/drivers/exynos-audss-clk/unbind
$ echo 381.audss-clock-controller
/sys/bus/platform/drivers/exynos-audss-clk/bind
[ 1463.044061]
While fixing audss clock access when domain is gated (commit clk:
samsung: Fix clock disable failure because domain being gated) generic
code from clk-gate/divider/mux was taken and modified.
This generic code leaks memory allocated for internal structures (struct
clk_gate/clk_divider/clk_mux).
The pinctrl for audio subsystem needs 'mau_epll' clock to be enabled in
order to properly access memory during GPIO setup.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git
Audio subsystem clocks are located in separate block. If clock for this
block (from main clock domain) 'mau_epll' is gated then any read or
write to audss registers will block.
This was observed on Exynos 5420 platforms (Arndale Octa and Peach
Pi/Pit) after introducing runtime PM to pl330 DMA
Hi,
Changes since v1
1. clocks-audss: Reimplement own clock register functions instead
changing clk API. Minor fixes. (after idea from Tomasz Figa)
2. Add new patches: fix for pinctrl and minor fixes in clk-audss.
Description
===
This patchset tries to solve
Dear Sir
Did your website get hit by Google Penguin update on October 17th 2014? What
basically is Google Penguin Update? It is actually a code name for Google
algorithm which aims at decreasing your websites search engine rankings that
violate Googles guidelines by using black hat SEO
Hello,
Heesub Shin heesub.s...@samsung.com writes:
Using the current exynos_defconfig on the exynos5422-odroid-xu3, only
6 of 8 CPUs come online with MCPM boot. CPU0 is an A7, CPUs 1-4 are
A15s and CPU5-7 are the other A7s, but with the current code, CPUs 5
and 7 do not boot:
[...]
Hello Krzysztof,
On 11/26/2014 03:24 PM, Krzysztof Kozlowski wrote:
Description
===
This patchset tries to solve dependency between AudioSS components
(clocks and GPIO) and main clock controller on Exynos platform.
This solves boot failure of Peach Pi/Pit and Arndale Octa [1].
I
On Wed, Nov 26, 2014 at 02:53:04PM +0530, Krishna Mohan Dani wrote:
Adding machine driver to instantiate I2S based realtek's ALC5631
sound card on Arndale board.
Applied, thanks.
signature.asc
Description: Digital signature
Hi Kevin,
On Wed, Nov 26, 2014 at 6:30 AM, Kevin Hilman khil...@kernel.org wrote:
Hi Abhilash,
Abhilash Kesavan kesavan.abhil...@gmail.com writes:
[...]
To be honest, since I don't have the exynos5420 arndale, chromebook...but
smdk
which has different bootloader, I couldn't test
: Amit Daniel Kachhap amit.dan...@samsung.com
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
v2:
- rebased on top of next-20141126 branch of linux-next kernel tree
(it also applies fine to for-next branch of linux-samsung.git
/pmu.o.after
Cc: Pankaj Dubey pankaj.du...@samsung.com
Cc: Amit Daniel Kachhap amit.dan...@samsung.com
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
v2:
- rebased on top of next-20141126 branch of linux-next kernel tree
On 11/24/14 19:57, Chanwoo Choi wrote:
This patchset adds the support of Exynos3250-based Monk board and Exynos-based
boards compatible string and description to remove build warning. Also, this
patchset includes a patch which remove unused dt node for command line in
Exynos3250-based Rinato
In this patch, the cpu_cooling code checks for the usability of cpufreq
layer before proceeding with the CPU cooling device registration. The
main reason is: CPU cooling device is not usable if cpufreq cannot
switch frequencies.
Similar checks are spread in thermal drivers. Thus, the advantage
Abhilash Kesavan kesavan.abhil...@gmail.com writes:
Hi Kevin,
On Wed, Nov 26, 2014 at 6:30 AM, Kevin Hilman khil...@kernel.org wrote:
Hi Abhilash,
Abhilash Kesavan kesavan.abhil...@gmail.com writes:
[...]
To be honest, since I don't have the exynos5420 arndale, chromebook...but
smdk
On 11/24/14 17:49, Lukasz Majewski wrote:
Hi Kukjin,
Lukasz Majewski wrote:
+ Bart, Tomasz and MLs
Hi Lukasz,
Please post including MLs, even resending.
Will apply for v3.19, and just note that you asked me to apply this
for 3.18 in personal talk but I couldn't see any requirements
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
DPMS only makes sense when the mode changes, for plane update changes do
not perform any dpms operation.
This move places the win_commit() and commit() calls directly in the code
instead of calling exynos_drm_crtc_commit() thus avoiding DPMS
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Avoid an extra call to exynos_drm_crtc_mode_set_commit() that only calls
exynos_update_plane().
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 8 ++--
1 file changed, 6
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
We can safely use the exynos_update_plane() to update the plane
framebuffer for both the overlay and primary planes.
Note that this patch removes a call to manager-ops-commit() in
exynos_drm_crtc_mode_set_commit(). The commit() call is used
On 11/27/14 02:56, Kevin Hilman wrote:
Abhilash Kesavan kesavan.abhil...@gmail.com writes:
Hi Kevin,
On Wed, Nov 26, 2014 at 6:30 AM, Kevin Hilman khil...@kernel.org wrote:
Hi Abhilash,
Abhilash Kesavan kesavan.abhil...@gmail.com writes:
[...]
To be honest, since I don't have the
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
It's doing nothing but calling exynos_crtc-ops-win_commit(), so let's
call this directly to avoid extra layers of abstraction.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 4
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
This series is try to unify all the paths on exynos DRM that handle plane
updates. Now SetPlane, PageFlip and SetCrtc (fb changed only) are all
processed by the same function: exynos_update_plane().
In the unify process the DPMS operations
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
DPMS settings should only be changed by a full modeset.
exynos_plane_update() should only care about updating the planes itself
and nothing else.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
This was just as extra chain in the call stack. We just rename it to
_set_base() and let it do everything alone.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 8 +---
1 file
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
We set it in the beginning of the function, thus no need to set it at
initialization.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 2 +-
1 file changed, 1 insertion(+), 1
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
vidi_commit does nothing, remove it and its callers.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_vidi.c | 12
1 file changed, 12 deletions(-)
diff --git
On Wed, Nov 26, 2014 at 02:26:07PM +0530, D Krishna Mohan wrote:
Following your suggestion I have sent a patch
(187024b36c635bd454c1b1587b58c9439d3a46ad on your git, branch: rt5631 )
using ifdef which you have already applied.
Since there are more suggestion asking for second (__maybe_unused)
Kevin Hilman khil...@kernel.org writes:
Hi Thomas,
Thomas Abraham thomas...@samsung.com writes:
Changes since v11:
- Rebased on top of git://linuxtv.org/snawrocki/samsung.git
for-v3.19-exynos-clk
Thanks for rebasing/reposting.
This patch series removes the use of Exynos4210 and
On Wed, 26 Nov 2014, Kevin Hilman wrote:
Abhilash Kesavan kesavan.abhil...@gmail.com writes:
Hi Kevin,
On Wed, Nov 26, 2014 at 6:30 AM, Kevin Hilman khil...@kernel.org wrote:
[...]
More specifically, with only the loopback call to turn off CCI commented
out, the imprecise aborts
On 11/24/14 17:47, Pankaj Dubey wrote:
This patch adds syscon based phandle to i2c device nodes of exynos5250
and exynos5420. These phandles will be used to save restore i2c sysreg
configuration register during s2r from i2c driver.
CC: Rob Herring robh...@kernel.org
CC: Randy Dunlap
On Mon, Nov 10, 2014 at 02:43:50PM +0100, Javier Martinez Canillas wrote:
Hello Mark,
This is the sixth version of the series that adds regulator initial
and suspend operating modes support. It relies on the existing work
that added suspend states bindings. The opmodes are parsed by the
On Thu, Nov 06, 2014 at 03:21:49PM +0530, Padmavathi Venna wrote:
Exynos7 SPI controller supports only the auto Selection of
CS toggle mode and Exynos7 SoC includes six SPI controllers.
Add support for these changes in Exynos7 SPI controller driver.
Applied, thanks. It does seem like these
On Tue, Nov 11, 2014 at 01:04:44PM +0100, Javier Martinez Canillas wrote:
The max77802 PMIC regulators output can be configured in one of two
modes: Output ON (normal) and Output ON in Low Power Mode. Some of
Applied, thanks.
signature.asc
Description: Digital signature
On Tue, Nov 11, 2014 at 01:04:43PM +0100, Javier Martinez Canillas wrote:
Some regulators from the max77802 PMIC support to be configured in one
of two operating mode: Output ON (normal) and Output On Low Power Mode.
Applied, thanks.
signature.asc
Description: Digital signature
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
'base' is more widely used name in the drm subsystem for the base object.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 4 ++--
drivers/gpu/drm/exynos/exynos_drm_drv.h | 7
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Get the pipe value from a parameter instead of getting it from
manager-pipe. We are removing manager-pipe.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 8
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Following the removal of struct exynos_drm_overlay we now remove the manager
one as well. This remove another abstrastraction layer from exynos drm.
We can now use known names like CRTC and Planes instead of manager and overlay.
This patchset
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
manager-drm_dev is only accessed by exynos_drm_crtc_create() so this patch
pass drm_dev as argument on exynos_drm_crtc_create() and remove it from
struct exynos_drm_manager.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
It is not longer used. This is part of the process of removing
struct exynos_drm_manager entirely.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 2 +-
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
'type' is now part of the struct exynos_drm_crtc. This is just another
step in the struct exynos_drm_manager removal.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 6 --
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
exynos_drm_manager was just a redundant struct to represent the crtc as
well. In this commit we merge exynos_drm_manager into exynos_drm_crtc to
remove an unnecessary level of indirection easing the understand of the
flow on exynos.
On 2014年11月25日 21:11, George Cherian wrote:
Pass the quir flag XHCI_DRD_SUPPORT from DWC3 host to xhci platform driver.
quir to quirk
Regards,
Baolu
This enables xhci driver to handle deallocation's differently while in DRD mode.
Pass the quirk flag XHCI_NEEDS_LHC_RESET from DWC3 host to
On Thursday 27 November 2014 12:13 AM, Kukjin Kim wrote:
On 11/24/14 17:47, Pankaj Dubey wrote:
This patch adds syscon based phandle to i2c device nodes of exynos5250
and exynos5420. These phandles will be used to save restore i2c sysreg
configuration register during s2r from i2c driver.
CC:
Few nits..
On 26 November 2014 at 23:20, Eduardo Valentin edubez...@gmail.com wrote:
Signed-off-by: Eduardo Valentin edubez...@gmail.com
---
The normal practice is to write the non-commitable part here ...
drivers/thermal/cpu_cooling.c | 5 +
Hi Arnd, Olof, Kevin
Please pull this branch for exynos7 SoC into arm-soc.
Note Greg agreed to upstream via arm-soc tree.
Thanks,
Kukjin
The following changes since commit f114040e3ea6e07372334ade75d1ee0775c355e1:
Linux 3.18-rc1 (2014-10-19 18:08:38 -0700)
are available in the git
The following changes since commit c645a598f99768e6cc82129081458dfdd0c273b7:
ARM: EXYNOS: Call regulator core suspend prepare and finish functions
(2014-11-21 22:49:47 +0900)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
The following changes since commit a427d15062ac46a00a22d2f0b9d05093c18ff2f1:
ARM: dts: Add micro SD card SDHCI node for exynos4412-trats
(2014-11-07 08:28:24 +0900)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
The following changes since commit 3b1f6f3450b6a64aead53d09fc6f8bba2999c450:
Merge remote-tracking branch 'arm-soc/cleanup/dts-subdirs' into
v3.19-next/dt-samsung-64 (2014-11-26 16:02:13 +0900)
are available in the git repository at:
Chander Kashyap wrote:
Exynos7 supports multiple idle states. Core power down is one such
idle state, where cores can be powered off independently.
This patch adds support for core power down idle state.
Entry latency for core power down idle state is calculated as follows:
1. Time
This patch adds missing divider/gate clocks of CMU_PERIC domain
which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
external input clock which has 'ioclk_*' prefix.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi
This patch adds the necessary Kconfig entries to enable
support for the ARMv8 based Exynos5433 SoC.
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
Acked-by: Inki Dae
This patch adds the mux/divider/gate clocks for CMU_AUD domain which
includes the clocks of Cortex-A6/Bus/Audio clocks.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
This patch adds ths mux/divider/gate clocksof CMU_G2D domain which includes
G2D/MDMA IPs. The CMU_G2D must need the clocks related to G2D by providing
CMU_TOP domain. So, this patch add several clocks for G2D from CMU_TOP domain.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa
This patch adds new s3c24xx_serial_drv_data structure for Exynos5433 SoC
because Exynos5433 has different fifo size from existing Exynos4 SoC.
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
Cc: Jiri Slaby jsl...@suse.cz
Cc: linux-ser...@vger.kernel.org
Signed-off-by: Chanwoo Choi
This patch adds the mux/divider/gate clocks for CMU_G3D domain which contains
the clocks for GPU(3D Graphics Engine).
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
From: Jaehoon Chung jh80.ch...@samsung.com
This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos5433
SoC. MSHC is an interface between the system the SD/MMC card.
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Arnd Bergmann a...@arndb.de
Cc:
This patch adds the mux/divider/gate clocks for CMU_FSYS domain which
contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
This patch adds the divider/gate of CMU_GSCL domain which contains gscaler
clocks.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim
This patch adds SPI (Serial Peripheral Interface) dt node for Exynos5433 SoC.
SPI transfers serial data by using various peripherals. SPI includes
8-bit/16-bit/32-bit shift registers to transmit and receive data. PDMA is used
for SPI communication.
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark
This patch adds the the mux/divider/gate clocks for CMU_DISP domain which
includes the clocks of Display IPs (DECON/HDMI/DSIM/MIXER). The CMU_DISP clocks
is used to need the source clock of CMU_MIF domain so, the CMU_MIF's clocks
related to CMU_DISP should be always on state.
Also, CMU_DISP must
This patchset adds new 64-bit Exynos5433 Samsung SoC which contains quad
Cortex-A57 and quad Cortex-A53. It is desigend with the 20nm low power process.
This patchset include some patches such as:
- Support booting of Exynos5433
- Support UART/MCT/GIC/HSI2C/SPI/PDMA/MSHC
- Support the clock
This patch adds missing gate clocks of CMU_PERIS domain
which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs.
The special clocks of CMU_PERIS use fin_pll source clock directly.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi
This patch adds the mux/divider/gate clock fo CMU_MIF domain which includes
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa
This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
which contain global data buses clocked at up the 400MHz. These blocks
transfer data between DRAM and various sub-blocks. These clock domains
also contain global peripheral buses clocked at 67/111/200/222/266/333/400
MHz and
This patch add binding documentation for Exynos5433 clock controller.
Exynos5433 has various clock domains So, this documentation explains
the detailed clock domains ans usage guide.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi
This patch adds driver data for Exynos5433 SoC. Exynos5433 includes 228 multi-
functional input/output port pins and 135 memory port pins. There are 41 general
port groups and 2 memory port groups.
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Thomas Abraham thomas.abra...@linaro.org
Cc: Linus
This patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433.
CMU_TOP domain provides source clocks to other CMU domains.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC
based on Octal core CPUs (quad Cortex-A57 and quad Cortex-A53).
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: Catalin Marinas
This patch adds the support for CMU (Clock Management Units) of Exynos5433
which is 64bit SoC and has Octa-cores. This patch supports necessary clocks
for kernel boot as following:
- PLL/MMC/UART/MCT/I2C/SPI
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
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