This patch remove unecessary property of gpio-keys node.
gpio-keys driver do not uses interrupts and interrupt-parent.
Cc: Kukjin Kim
Cc: Youngjun Cho
Cc: Chanwoo Choi
Reviewed-by: Chanwoo Choi
Signed-off-by: Beomho Seo
---
arch/arm/boot/dts/exynos3250-monk.dts |2 --
arch/arm/boot/dts
This patch replace number by macro in gpio keys for exynos 3250 boards.
Cc: Kukjin Kim
Cc: Youngjun Cho
Cc: Chanwoo Choi
Reviewed-by: Chanwoo Choi
Signed-off-by: Beomho Seo
---
arch/arm/boot/dts/exynos3250-monk.dts |3 ++-
arch/arm/boot/dts/exynos3250-rinato.dts |3 ++-
2 files cha
This patch revises property of gpio-keys node.
The first patch remove unecessary property.
And then, replace by macro in gpio keys.
Beomho Seo (2):
ARM: dts: exynos3250: remove unecessary property of gpio-keys node
ARM: dts: exynos3250: replace number by macro in gpio keys
arch/arm/boot/dts/
Genlty Ping.
Best Regards,
Chanwoo Choi
On 12/29/2014 09:04 AM, Chanwoo Choi wrote:
> This patchset add new devfreq_event class to provide raw data to determine
> current utilization of device which is used for devfreq governor.
>
> [Description of devfreq-event class]
> This patchset add new d
Gently Ping.
Best Regards,
Chanwoo Choi
On 12/17/2014 08:46 AM, Chanwoo Choi wrote:
> This patch adds the support for Exynos 64bit SoC. The delay_timer is only used
> for Exynos 32bit SoC.
>
> Cc: Daniel Lezcano
> Cc: Thomas Gleixner
> Cc: Kukjin Kim
> Cc: Mark Rutland
> Signed-off-by: Chanw
Alim,
On Sun, Jan 4, 2015 at 2:43 PM, Alim Akhtar wrote:
>> You are breaking backward compatibility here. If your change is
>> merged then all old boards will instantly break. Since the "dts" and
>> code changes will likely be merged through different trees you'll end
>> up with a bunch of brok
Dear all,
On Tue, 06 Jan 2015 00:21:22 +0900
Inki Dae wrote:
> On 2015년 01월 05일 23:19, Thierry Reding wrote:
> > On Wed, Dec 31, 2014 at 07:41:43PM +0900, Inki Dae wrote:
> >> Hi Thierry,
> >>
> >> Ping~.
> >>
> >> Or is it ok to pick up this patch to my tree, exynos-drm-next? It
> >> doesn't se
Hi,
On Sat, Jan 03, 2015 at 08:53:45PM +0100, Lukasz Majewski wrote:
> >
> > Apologize for late answer.
>
> I will be able to address your comments no sooner than next Monday.
> Moreover I still believe that we will manage to add this code to your
> -next branch :-)
Good! Take your time.
C
On Monday 05 January 2015 13:19:00 Marek Szyprowski wrote:
> DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
> + .l2c_aux_val= OMAP_L2C_AUX_CTRL,
> + .l2c_aux_mask = 0xcf9f,
> + .l2c_write_sec = omap4_l2c310_write_sec,
> .reserve= om
> From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
> Sent: Wednesday, December 17, 2014 5:50 AM
>
> DWC2 module on Exynos SoCs is used only as peripheral controller (UDC),
> so add support for selecting default initial state for dual-role mode. The
> default init mode can be overridden by
On 13:19-20150105, Marek Szyprowski wrote:
> All four register for latency and filter settings cannot be written in
> non-secure mode and they should go through l2c_write_sec(). More on this
> can be found in CoreLink Level 2 Cache Controller L2C-310 Technical
> Reference Manual, 3
On 13:19-20150105, Marek Szyprowski wrote:
> From: Tomasz Figa
>
> Certain implementations of secure hypervisors (namely the one found on
> Samsung Exynos-based boards) do not provide access to individual L2C
> registers. This makes the .write_sec()-based interface insufficient
On 01/05/2015 06:18 AM, Marek Szyprowski wrote:
> This is an updated patchset, which intends to add support for L2 cache
> on Exynos4 SoCs on boards running under secure firmware, which requires
> certain initialization steps to be done with help of firmware, as
> selected registers are writable on
* Marek Szyprowski [150105 04:22]:
> From: Tomasz Figa
>
> Certain platforms (i.e. Exynos) might need to set .write_sec callback
> from firmware initialization which is happenning in .init_early callback
> of machine descriptor. However current code will overwrite the pointer
> with whatever is
* Marek Szyprowski [150105 04:22]:
> From: Tomasz Figa
>
> Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
> settings configured in registers leading to crashes if L2C is enabled
> without overriding them. This patch introduces bindings to enable
> prefetch settings
* Marek Szyprowski [150105 04:22]:
> From: Tomasz Figa
>
> Because certain secure hypervisor do not allow writes to individual L2C
> registers, but rather expect set of parameters to be passed as argument
> to secure monitor calls, there is a need to provide an interface for the
> L2C driver to
* Marek Szyprowski [150105 04:22]:
> From: Tomasz Figa
>
> Certain implementations of secure hypervisors (namely the one found on
> Samsung Exynos-based boards) do not provide access to individual L2C
> registers. This makes the .write_sec()-based interface insufficient and
> provoking ugly hack
* Marek Szyprowski [150105 04:22]:
> All four register for latency and filter settings cannot be written in
> non-secure mode and they should go through l2c_write_sec(). More on this
> can be found in CoreLink Level 2 Cache Controller L2C-310 Technical
> Reference Manual, 3.2. Register summary, ta
* Marek Szyprowski [150105 04:22]:
> This patch implements generic DT L2C initialisation (the one from
> init_IRQ in arch/arm/kernel/irq.c) for Omap4 and AM43 platforms and
> kills the SoC specific stuff in arch/arm/mach-omap2/omap4-common.c.
>
> Signed-off-by: Marek Szyprowski
Seems to work ju
On Mon, Jan 05, 2015 at 08:25:16PM +0900, Inha Song wrote:
> + - clocks : Reference to the codec master clock
> + - clock-names : The clock should be named "mclk"
This should be done in the CODEC driver, not in the machine driver - the
CODEC always needs the clock, it's not something specific to
Just resend it with Thierry's request.
Thanks,
Inki Dae
Original Message
Subject: [PATCH v2 2/3] drm/panel: add s6e63j0x03 LCD panel driver
Date: Tue, 09 Dec 2014 18:29:05 +0900
From: Hyungwon Hwang
To: dri-de...@lists.freedesktop.org
CC: airl...@linux.ie, devicet...@vger.kern
On 2015년 01월 05일 23:19, Thierry Reding wrote:
> On Wed, Dec 31, 2014 at 07:41:43PM +0900, Inki Dae wrote:
>> Hi Thierry,
>>
>> Ping~.
>>
>> Or is it ok to pick up this patch to my tree, exynos-drm-next? It
>> doesn't seem to care for a long time.
>
> I don't seem to have a copy of the v2 2/3 patch
On Mon, 2015-01-05 at 17:18 +0900, Joonyoung Shim wrote:
> Hi Sjoerd,
>
> On 12/05/2014 04:27 AM, Sjoerd Simons wrote:
> > Add DTS for the Hardkernel Odroid XU3. The name of the DTS file is kept the
> > same as the vendors naming, which means it's prefixed with exynos5422
> > instead of exynos5800
On Wed, Dec 31, 2014 at 07:41:43PM +0900, Inki Dae wrote:
> Hi Thierry,
>
> Ping~.
>
> Or is it ok to pick up this patch to my tree, exynos-drm-next? It
> doesn't seem to care for a long time.
I don't seem to have a copy of the v2 2/3 patch. All I found in my inbox
is the v2 0/3 cover-letter. Pl
On pon, 2015-01-05 at 15:05 +0100, Linus Walleij wrote:
> On Fri, Dec 5, 2014 at 12:00 PM, Krzysztof Kozlowski
> wrote:
>
> > The audio subsystem on Exynos 5420 has separate clocks and GPIO. To
> > operate properly on GPIOs the main block clock 'mau_epll' must be
> > enabled.
> >
> > This was obs
On Fri, Dec 5, 2014 at 12:00 PM, Krzysztof Kozlowski
wrote:
> The audio subsystem on Exynos 5420 has separate clocks and GPIO. To
> operate properly on GPIOs the main block clock 'mau_epll' must be
> enabled.
>
> This was observed on Peach Pi/Pit and Arndale Octa (after enabling i2s0)
> after int
On Fri, Jan 02, 2015 at 01:10:14PM +, Daniel Stone wrote:
> Hi Ajay,
>
> On 17 December 2014 at 09:31, Javier Martinez Canillas <
> javier.marti...@collabora.co.uk> wrote:
>
> > On 12/16/2014 12:37 AM, Laurent Pinchart wrote:
> > >> You asked Ajay to change his series to use the video port an
Hello Kukjin,
On Mon, Jan 5, 2015 at 2:20 PM, Kukjin Kim wrote:
> Javier Martinez Canillas wrote:
>>
>> I hope he can merge those patches as 3.19 fixes during the -rc cycle
>> to avoid having another kernel release with a non-working display on
>> Exynos5 boards.
>>
> Hi,
>
> Hmm...Probably I've
Hello Kukjin,
>>
>> Hello Kukjin,
>>
> Hi Javier,
>
> Happy new year :)
>
Thanks, happy new year for you as well!
>> You dropped this patch since exynos drm was causing boot hangs on some
>> platforms but the fix for that issue is already in linux-next (commit:
>> f1e9203 clk: samsung: Fix Ex
Javier Martinez Canillas wrote:
>
> [adding Kukjin and Vivek as cc]
>
> Hello Paolo,
>
> On Tue, Dec 23, 2014 at 11:16 AM, Paolo Pisati wrote:
> > Hi,
> >
> > 3.19-rc1 still misses these two patches:
> >
> > 156823e arm: dts: Exynos5: Use pmu_system_controller phandle for dp phy
> > 03c16e7 ARM
Pankaj Dubey wrote:
>
> As all these code has been moved into i2c driver, now we can
> safely remove them from machine files.
>
> CC: Russell King
> Signed-off-by: Pankaj Dubey
> ---
> This patch is leftover patch from patch series [1], resending it after
> rebasing.
> It can be cleanly applie
Javier Martinez Canillas wrote:
>
> Many Exynos devices have a display panel. Most of them just have
> a simple panel while others have more complex configurations that
> requires an embedded DisplayPort (eDP) to LVDS bridges.
>
> This patch enables the following features to be built in the kerne
Hi,
Thanks for your comments.
> Hi,
>
> A few small comments inline.
>
> On 01/05/2015 12:25 PM, Inha Song wrote:
> > --- /dev/null
> > +++ b/sound/soc/samsung/trats2_wm1811.c
> > @@ -0,0 +1,216 @@
> >[...]
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#includ
From: Tomasz Figa
Certain platforms (i.e. Exynos) might need to set .write_sec callback
from firmware initialization which is happenning in .init_early callback
of machine descriptor. However current code will overwrite the pointer
with whatever is present in machine descriptor, even though it ca
From: Tomasz Figa
Because certain secure hypervisor do not allow writes to individual L2C
registers, but rather expect set of parameters to be passed as argument
to secure monitor calls, there is a need to provide an interface for the
L2C driver to ask the firmware to configure the hardware accor
From: Tomasz Figa
Certain implementations of secure hypervisors (namely the one found on
Samsung Exynos-based boards) do not provide access to individual L2C
registers. This makes the .write_sec()-based interface insufficient and
provoking ugly hacks.
This patch is first step to make the driver
This patch implements generic DT L2C initialisation (the one from
init_IRQ in arch/arm/kernel/irq.c) for Omap4 and AM43 platforms and
kills the SoC specific stuff in arch/arm/mach-omap2/omap4-common.c.
Signed-off-by: Marek Szyprowski
---
arch/arm/mach-omap2/board-generic.c | 6 ++
arch/arm/
All four register for latency and filter settings cannot be written in
non-secure mode and they should go through l2c_write_sec(). More on this
can be found in CoreLink Level 2 Cache Controller L2C-310 Technical
Reference Manual, 3.2. Register summary, table 3.1. This have been checked
the TRM for
From: Tomasz Figa
Exynos4 SoCs equipped with an L2C-310 cache controller and running under
secure firmware require certain registers of aforementioned IP to be
accessed only from secure mode. This means that SMC calls are required
for certain register writes. To handle this, an implementation of
From: Tomasz Figa
Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
settings configured in registers leading to crashes if L2C is enabled
without overriding them. This patch introduces bindings to enable
prefetch settings to be specified from DT and necessary support in
From: Tomasz Figa
On Exynos SoCs it is necessary to resume operation of L2C early in
assembly code, because otherwise certain systems will crash. This patch
adds necessary code to non-secure resume handler.
Signed-off-by: Tomasz Figa
[rewrote the code accessing l2x0_saved_regs]
Sigend-off-by: M
From: Tomasz Figa
This patch adds device tree nodes for L2 cache controller present on
Exynos4 SoCs.
Signed-off-by: Tomasz Figa
Signed-off-by: Marek Szyprowski
Acked-by: Arnd Bergmann
Acked-by: Kukjin Kim
---
arch/arm/boot/dts/exynos4210.dtsi | 9 +
arch/arm/boot/dts/exynos4x12.dts
This is an updated patchset, which intends to add support for L2 cache
on Exynos4 SoCs on boards running under secure firmware, which requires
certain initialization steps to be done with help of firmware, as
selected registers are writable only from secure mode.
First patch updates Omap2+ platfor
On 1/5/15, Kukjin Kim wrote:
> Ming Lei wrote:
>>
>> Hi Guys,
>>
> Hi,
>
> Sorry for late response.
>
>> On Thu, Dec 25, 2014 at 6:32 PM, Pankaj Dubey
>> wrote:
>> > +CC: Thomas Abraham
>> >
>> > Hi Ming,
>> >
>> > On Thursday 25 December 2014 02:18 PM, Ming Lei wrote:
>> >>
>> >> Hi Pankaj,
>> >
Hi,
The patchset adds:
1. a way of parsing custom DT properties by the driver when simplified
DT parsing method is used,
2. GPIO enable control to the max77686 driver.
Rationale
=
After converting drivers to simplified DT parsing method, the parsing
is done by regulator core. The dri
Add enable control over GPIO for regulators supporting this: LDO20,
LDO21, LDO22, buck8 and buck9.
This is needed for proper (and full) configuration of the Maxim 77686
PMIC without creating redundant 'regulator-fixed' entries.
Signed-off-by: Krzysztof Kozlowski
---
drivers/regulator/max77686.c
Copy the 'regulator_config' structure passed to regulator_register()
function so the driver could safely modify it after parsing init data.
The driver may want to change the config as a result of specific init
data parsed by regulator core (e.g. when core handled parsing device
tree).
Signed-off-
Document usage of maxim,ena-gpios properties which turn on external/GPIO
control over regulator.
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/mfd/max77686.txt | 14 ++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/max
Remove fixed regulators (duplicating what max77686 provides) and
add GPIO enable control to max77686 regulators.
This gives the system full control over those regulators. Previously
the state of such regulators was a mixture of what max77686 driver set
over I2C and what regulator-fixed set through
When drivers use simplified DT parsing method (they provide
'regulator_desc.of_match') they still may want to parse custom
properties for some of the regulators. For example some of the
regulators support GPIO enable control.
Add a driver-supplied callback for such case. This way the regulator
cor
Hi,
A few small comments inline.
On 01/05/2015 12:25 PM, Inha Song wrote:
--- /dev/null
+++ b/sound/soc/samsung/trats2_wm1811.c
@@ -0,0 +1,216 @@
[...]
+#include
+#include
+#include
+#include
+#include
+#include "i2s.h"
+#include "i2s-regs.h"
You probably don't need i2s-regs.h
+#includ
On Mon, Jan 05, 2015 at 12:09:03PM +0100, Krzysztof Kozlowski wrote:
> Thanks, but... Few days after my patch Mark Brown posted something
> similar:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2014-December/310743.html
>
> It was merged by Arnd Bergman and sent to Linus around 3.19-rc1
This patch add Trats2 audio subsystem bindings document.
Signed-off-by: Inha Song
---
.../bindings/sound/samsung,trats2-wm1811.txt | 31 ++
1 file changed, 31 insertions(+)
create mode 100644
Documentation/devicetree/bindings/sound/samsung,trats2-wm1811.txt
diff --gi
This patch add the sound machine driver for Trats2 board.
The codec operate in master mode. So, Reference to the
codec master clock must be defined in DT.
Signed-off-by: Inha Song
---
sound/soc/samsung/Kconfig | 8 ++
sound/soc/samsung/Makefile| 2 +
sound/soc/samsung/trats2_
This patch add WM1811 audio codec, I2S interface and the sound
machine nodes to enable audio on exynos4412-trats2 board.
Signed-off-by: Inha Song
---
arch/arm/boot/dts/exynos4412-trats2.dts | 38 +
1 file changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/e
This patch-set adds basic sound support for the Trats2 boards.
It just support primary I2s and external speaker playback.
Inha Song (3):
ASoC: samsung: Add machine driver for Trats2
ASoC: samsung: Document Trats2 audio subsystem bindings
ARM: dts: Add sound nodes for exynos4412-trats2
.../
On pon, 2015-01-05 at 12:03 +0100, Joerg Roedel wrote:
> On Fri, Dec 05, 2014 at 02:47:37PM +0100, Krzysztof Kozlowski wrote:
> > drivers/iommu/Kconfig | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Applied to iommu/fixes, thanks.
Thanks, but... Few days after my patch Mark Brown
On Fri, Dec 05, 2014 at 02:47:37PM +0100, Krzysztof Kozlowski wrote:
> drivers/iommu/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied to iommu/fixes, thanks.
--
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the body of a message to majord.
Hey Lukasz,
Blame the holiday season for my late reply ;)
On Fri, 2014-12-19 at 17:13 +0100, Lukasz Majewski wrote:
> Hi Guenter,
>
> > On Fri, Dec 19, 2014 at 04:32:24PM +0100, Lukasz Majewski wrote:
> > > Hi Sjoerd,
> > >
> > > Thanks for your feedback and sorry for a late reply.
> > >
> > >
Ming Lei wrote:
>
> Hi Guys,
>
Hi,
Sorry for late response.
> On Thu, Dec 25, 2014 at 6:32 PM, Pankaj Dubey
> wrote:
> > +CC: Thomas Abraham
> >
> > Hi Ming,
> >
> > On Thursday 25 December 2014 02:18 PM, Ming Lei wrote:
> >>
> >> Hi Pankaj,
> >>
> >> In your commit fce9e5bb2(ARM: EXYNOS: Ad
Hi,
On Monday 05 January 2015 03:22 PM, Sjoerd Simons wrote:
On Mon, 2015-01-05 at 14:44 +0530, Pankaj Dubey wrote:
Commit id: 2e94ac42898f84d76e3c21dd91bc is not taking care
of mapping of exynos5440 PMU register which will result in kernel panic
on exynos5440.
As exynos5440 DTS does not have
The common clk_register_{divider,gate,mux} functions allocated memory
for internal data which wasn't freed anywhere. Drivers using these
helpers could only unregister clocks but the memory would still leak.
Add corresponding unregister functions which will release all resources.
Signed-off-by: Kr
The memory allocated by basic clock divider/gate/mux (struct clk_gate,
clk_divider and clk_mux) was leaking. During driver unbind or probe
failure the driver only unregistered the clocks.
Use clk_unregister_{gate,divider,mux} to release all resources.
Signed-off-by: Krzysztof Kozlowski
---
driv
On Mon, 2015-01-05 at 14:44 +0530, Pankaj Dubey wrote:
> Commit id: 2e94ac42898f84d76e3c21dd91bc is not taking care
> of mapping of exynos5440 PMU register which will result in kernel panic
> on exynos5440.
>
> As exynos5440 DTS does not have PMU node, and also we are skipping
> exynos_pm_init in
Gentle Ping.
On Wednesday 03 December 2014 01:14 PM, Pankaj Dubey wrote:
Exynos SoC's DT files are using Chipid device nodes, but it's binding
information is missing. This patch adds exynos-chipid binding information.
Signed-off-by: Pankaj Dubey
---
.../bindings/arm/samsung/exynos-chipid.txt
As all these code has been moved into i2c driver, now we can
safely remove them from machine files.
CC: Russell King
Signed-off-by: Pankaj Dubey
---
This patch is leftover patch from patch series [1], resending it after rebasing.
It can be cleanly applied on kgene/for-next and linux-next/next-20
Commit id: 2e94ac42898f84d76e3c21dd91bc is not taking care
of mapping of exynos5440 PMU register which will result in kernel panic
on exynos5440.
As exynos5440 DTS does not have PMU node, and also we are skipping
exynos_pm_init in case of exynos5440, let's avoid mapping of exynos5440 PMU.
Reporte
Hello Krzysztof,
>> Hello Kukjin,
>>
>> You dropped this patch since exynos drm was causing boot hangs on some
>> platforms but the fix for that issue is already in linux-next (commit:
>> f1e9203 clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable
>> failure due to domain being gated) s
On pią, 2015-01-02 at 17:11 +0100, Javier Martinez Canillas wrote:
> Many Exynos devices have a display panel. Most of them just have
> a simple panel while others have more complex configurations that
> requires an embedded DisplayPort (eDP) to LVDS bridges.
>
> This patch enables the following f
Hi Sjoerd,
On 12/05/2014 04:27 AM, Sjoerd Simons wrote:
> Add DTS for the Hardkernel Odroid XU3. The name of the DTS file is kept the
> same as the vendors naming, which means it's prefixed with exynos5422
> instead of exynos5800 as the SoC name even though it includes the
> exyno5800 dtsi.
>
> S
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