Hi Abhilash,
On Wednesday 10 December 2014 10:46 AM, Sudeep Holla wrote:
On Wednesday 10 December 2014 09:55 AM, Abhilash Kesavan wrote:
Hi Sudeep,
On Wed, Dec 10, 2014 at 9:44 AM, Sudeep Holla wrote:
Hi Abhilash,
On Wednesday 10 December 2014 09:31 AM, Abhilash Kesavan wrote:
Hi,
On F
On 2015년 01월 08일 03:06, Gustavo Padovan wrote:
> 2014-12-26 Inki Dae :
>
>> On 2014년 12월 22일 22:04, Gustavo Padovan wrote:
>>> Hi Dave,
>>>
>>> Here goes a bunch of clean up for the exynos driver. I've posted this work
>>> in
>>> the mailing list twice but never got a review on it, first time was
On 17:42-20150107, Marc Zyngier wrote:
> As for the patches, they are on top of 3.19-rc3.
Applied the 21 patches and gave a quick dry run on various boards
BASE = v3.19-rc3 + 1 uImage+dtb patch for
IRQ = v3.19-rc3 + irq series
NOTE: I am yet to dig in deeper to figure out which platform may h
This patch adds the support for suspend-to-ram feature of Exynos3250 SoC.
Exynos3250 don't contain the L2 cache.
Cc: Kukjin Kim
Signed-off-by: Chanwoo Choi
Acked-by: Kyungmin Park
---
Depend on:
- v3.19-rc3
arch/arm/mach-exynos/regs-pmu.h | 3 ++
arch/arm/mach-exynos/suspend.c | 77
On 12/31/2014 03:43 PM, Alim Akhtar wrote:
> From: Seungwon Jeon
>
> Implements HS400 support for exynos host driver.
> And this patch includes some updates as new mode is added.
>
> Signed-off-by: Seungwon Jeon
> Signed-off-by: Alim Akhtar
> ---
> .../devicetree/bindings/mmc/exynos-dw-mshc.t
This patch adds the divider clock id for Exynos4 memory bus frequency.
The clock id is used fo DVFS (Dynamic Voltage/Frequency Scaling)
feature of exynos memory bus frequency.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
---
drivers/clk/samsung/clk-exynos4.c | 10 +-
This patch adds the Exynos4412 memory-bus node which includes the regulator
and devfreq-event phandle. The devfreq-event phandle is used for the
governor of devfreq device and provide the current usage state of
MIF (Memory Interface) / INT (Internal) memory bus group.
Cc: Kukjin Kim
Cc: Myungjoo
This patch adds the memory bus node for Exynos3250 SoC. Exynos3250 has
following memory buses to translate data between DRAM and eMMC/sub-IPs.
Following list specifies the detailed relation between memory bus clock and DMC
IP in MIF (Memory Interface) block:
- DMC clock : DMC (Dynamic Memory Contr
This patch adds the generic exynos bus frequency driver for memory bus
with DEVFREQ framework. The Samsung Exynos SoCs have the common architecture
for memory bus between DRAM memory and MMC/sub IP in SoC. This driver can
support the memory bus frequency driver for Exynos SoCs.
Each memory bus blo
This patch adds the documentation for generic exynos memory bus frequency
driver.
Cc: MyungJoo Ham
Cc: Kyungmin Park
Cc: Kukjin Kim
Signed-off-by: Chanwoo Choi
---
.../devicetree/bindings/devfreq/exynos-busfreq.txt | 184 +
1 file changed, 184 insertions(+)
create mode 10
This patch-set adds the generic exynos bus frequency driver for memory bus
with DEVFREQ framework. The Samsung Exynos SoCs have the common architecture
for memory bus between DRAM memory and MMC/sub IP in SoC. This driver can
support the memory bus frequency driver for Exynos SoCs.
Each memory bus
This patch adds the memory bus node for Exynos4210 SoC. Exynos4210 SoC has
one memory bus to translate data between DRAM and eMMC/sub-IPs because
Exynos4210 must need only one regulator for memory bus.
Following list specifies the detailed relation between memory bus clock and
sub-IPs:
- DMC/ACP c
This patch adds the Exynos3250 memory-bus node which includes the regulator
and devfreq-event phandle. The devfreq-event phandle is used for the
governor of devfreq device and provide the current usage state of
MIF (Memory Interface) / INT (Internal) memory bus group.
Cc: Kukjin Kim
Cc: Myungjoo
This patch adds the memory bus node for Exynos4x12 SoC. Exynos4x12 SoC has
two memory bus to translate data between DRAM and eMMC/sub-IPs.
Following list specifies the detailed relation between memory bus clock and DMC
IP in MIF (Memory Interface) block:
- DMC/ACP clock : DMC (Dynamic Memory Contr
Hi,
On 12/31/2014 03:43 PM, Alim Akhtar wrote:
> From: Seungwon Jeon
>
> ciu_div may not be common value for all speed mode.
> So, it needs to be attached to CLKSEL timing.
> This also introduce a new compatibale 'dw-mshc-hs200-timing'
> for selecting hs200 timing value
>
> Signed-off-by: Seun
This patch add PPMU (Platform Performance Monitoring Unit) dt node
to estimate the utilization of each IP in Exynos SoC throught DEVFREQ Event
subsystem.
This patch adds following PPMU dt nodes:
- PPMU_DMC0 0x106a
- PPMU_DMC1 0x106b
- PPMU_RIGHTBUS 0x112A
- PPMU_LEFTBUS 0x116A
This patch add the resource-managed function for devfreq-event device as
following functions. The devm_devfreq_event_add_edev() manages automatically
the memory of devfreq-event device using resource management.
- devm_devfreq_event_add_edev()
- devm_devfreq_event_remove_edev()
Cc: Myungjoo Ham
C
This patch add PPMU dt node to Exynos3250-base Rinato/Monk board. The PPMU node
is used to get the utilization of DMC0/DMC1/LEFTBUS/RIGHTBUS Block.
Cc: Kukjin Kim
Signed-off-by: Chanwoo Choi
Acked-by: Kyungmin Park
---
arch/arm/boot/dts/exynos3250-monk.dts | 40 ++
This patch adds PPMU (Performance Profiling Monitoring Unit) dt node
Exynos5260 SoC.
Exynos5260 SoC has following PPMU IPs:
- PPMU_DREX0_S0 0x10c6
- PPMU_DREX0_S1 0x10c7
- PPMU_DREX1_S0 0x10c8
- PPMU_DREX1_S1 0x10c9
- PPMU_EAGLE0x10cc
- PPMU_KFC 0x10cd
- PPMU_MFC
This patch adds the list of supported devfreq-event type as following.
Each devfreq-event device driver would support the various devfreq-event type
for devfreq governor at the same time.
- DEVFREQ_EVENT_TYPE_RAW_DATA
- DEVFREQ_EVENT_TYPE_UTILIZATION
- DEVFREQ_EVENT_TYPE_BANDWIDTH
- DEVFREQ_EVENT_T
This patch adds the documentation for Exynos PPMU (Platform Performance
Monitoring Unit) devfreq-event driver.
Cc: MyungJoo Ham
Cc: Kyungmin Park
Signed-off-by: Chanwoo Choi
---
.../bindings/devfreq/event/exynos-ppmu.txt | 110 +
1 file changed, 110 insertions(+)
c
This patch add dt node for PPMU_{DMC0|DMC1|LEFTBUS|RIGHTBUS} for
exynos4412-trats2 board. Each PPMU dt node includes one event of 'PPMU Count3'.
Cc: Kukjin Kim
Cc: Myungjoo Ham
Cc: Kyungmin Park
Signed-off-by: Chanwoo Choi
---
arch/arm/boot/dts/exynos4412-trats2.dts | 40 +
This patch adds exynos-ppmu devfreq-event driver to get performance data
of each IP for Samsung Exynos SoC. These event from Exynos PPMU provide
useful information about the behavior of the SoC that you can use when
analyzing system performance, and made visible and can be counted using
logic in ea
This patch add new devfreq_event class for devfreq_event device which provide
raw data (e.g., memory bus utilization/GPU utilization). This raw data from
devfreq_event data would be used for the governor of devfreq subsystem.
- devfreq_event device : Provide raw data for governor of existing devfre
This patch add PPMU (Platform Performance Monitoring Unit) dt node for Exynos4
(Exynos4210/4212/4412) SoC. PPMU dt node is used to monitor the utilization of
each IP.
The Exynos4210/Exynos4212/Exynos4412 SoC includes following PPMUs:
- PPMU_DMC0 0x106A_
- PPMU_DMC1 0x106B_
- PPMU
This patchset add new devfreq_event class to provide raw data to determine
current utilization of device which is used for devfreq governor.
The following description explains the feature of two kind of devfreq class:
- devfreq class (existing)
: devfreq consumer device use raw data from devfreq
eduling across all 8.
I tried v1.0 of the Odroid-XU3 DTB patch, applied to linux-next 20150107. I'm
only seeing 1 core running on my Odroid-XU3. The USB 3.0 port works (great!)
but I'm not getting any HDMI output. I didn't try DisplayPort. I'll gladly
try v2 of the patch on an XU3; is there a better base to apply the patch to?
Also setup memory allocations for version 8 of the MFC as present in
Samsung Exynos 5422/5800 SoCs
Signed-off-by: Sjoerd Simons
---
arch/arm/mach-exynos/exynos.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index c13d083..b343a
When disabling the samsung PWM the output state remains at the level it
was in the end of a pwm cycle. In other words, calling pwm_disable when
at 100% duty will keep the output active, while at all other setting the
output will go/stay inactive. On top of that the samsung PWM settings are
double-b
Add DTS for the Hardkernel Odroid XU3. The name of the DTS file is kept the
same as the vendors naming, which means it's prefixed with exynos5422
instead of exynos5800 as the SoC name even though it includes the
exyno5800 dtsi.
Signed-off-by: Sjoerd Simons
---
Changes since v1:
* Add chosen/linu
On Wed, 2015-01-07 at 18:37 +, Anand Moon wrote:
> Hi Sjoerd,
>
> I am using 3.18.0 kernel on my odroidxu3 board.
> Using exynos_defconfig I am able to boot the board.
>
> Are you able to get all the 8 core CPU up and running ?
>
>
> Only 4 core cpu's are on my board. Also CpuFreq is not wo
2014-12-30 Inki Dae :
> On 2014년 12월 18일 22:58, Gustavo Padovan wrote:
> > From: Gustavo Padovan
> >
> > Add CRTC callbacks .atomic_begin() .atomic_flush(). On exynos they
> > unprotect the windows before the commit and protects it after based on
> > a plane mask tha store which plane will be up
2014-12-30 Inki Dae :
> On 2014년 12월 18일 22:58, Gustavo Padovan wrote:
> > From: Gustavo Padovan
> >
> > The atomic helper to disable planes also uses exynos_update_plane() to
> > disable plane so we had to adapt it to both commit and disable planes.
> >
> > A check for NULL CRTC was added to e
Marc,
On 1/7/2015 9:42 AM, Marc Zyngier wrote:
The gic_arch_extn hack that a number of platform use has been nagging
me for too long. It is only there for the benefit of a few platform,
and yet it impacts all GIC users. Moreover, it gives people the wrong
idea ("let's use it to put some new cust
2014-12-26 Inki Dae :
> On 2014년 12월 22일 22:04, Gustavo Padovan wrote:
> > Hi Dave,
> >
> > Here goes a bunch of clean up for the exynos driver. I've posted this work
> > in
> > the mailing list twice but never got a review on it, first time was about a
>
> Never no. I already had a review and t
A common use of gic_arch_extn is to set up additional flags
to the GIC irqchip. It looks like a benign enough hack that
doesn't really require the users of that feature to be converted
to stacked domains.
Add a gic_set_irqchip_flags() function that platform code can
call instead of using the dread
Instead of directly touching gic_arch_extn, which is about to
be removed, use gic_set_irqchip_flags instead.
Signed-off-by: Marc Zyngier
---
arch/arm/mach-zynq/common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
i
Document the fact that some Exynos PMUs are capable of acting as
an interrupt controller.
Signed-off-by: Marc Zyngier
---
Documentation/devicetree/bindings/arm/samsung/pmu.txt | 13 +
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
Instead of directly touching gic_arch_extn, which is about to
be removed, use gic_set_irqchip_flags instead.
Acked-by: Linus Walleij
Signed-off-by: Marc Zyngier
---
arch/arm/mach-ux500/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm
OMAP4/5 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lyi
Nobody will regret it.
Signed-off-by: Marc Zyngier
---
Documentation/devicetree/bindings/arm/gic.txt | 6 --
1 file changed, 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt
b/Documentation/devicetree/bindings/arm/gic.txt
index 8112d0c..631cb71 100644
--- a/Documen
shmobile only uses gic_arch_extn.irq_set_wake to prevent the GIC
from returning -ENXIO when receiving a wake-up configuration request.
It is a lot simpler to tell the irq layer that we don't need any
configuration by using the IRQCHIP_SKIP_SET_WAKE, thanks to the
new gic_set_irqchip_flags function
IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying
Signed-off-by: Marc Zyngier
---
.../interrupt-controller/ti,omap4-wugen-mpu| 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
diff --git
a/Documentation/devicetree/bindings/interrup
Now that the users of gic_arch_extn have been fixed, drop the
"feature" for good. This leads to the removal of some now useless
locking.
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic.c | 54 -
include/linux/irqchip/arm-gic.h | 2 --
2 file
Exynos has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lyin
Tegra's LIC (Legacy Interrupt Controller) has been so far only
supported as a weird extension of the GIC, which is not exactly
pretty.
The stacked irq domain framework fits this pretty well, and allows
the LIC code to be turned into a standalone irqchip. In the process,
make the driver DT aware, s
This proves to be usefull with stacked domains, when the current
domain doesn't implement wake-up, but expect the parent to do so.
Signed-off-by: Marc Zyngier
---
include/linux/irq.h | 1 +
kernel/irq/chip.c | 16
2 files changed, 17 insertions(+)
diff --git a/include/linux/
Support for the TI crossbar used on the DRA7 family of chips
is implemented as an ugly hack on the side of the GIC.
Converting it to stacked domains makes it slightly more
palatable, as it results in a cleanup.
Unfortunately, as the DT bindings failed to acknowledge the
fact that this is actually
Signed-off-by: Marc Zyngier
---
.../interrupt-controller/nvidia,tegra-ictlr.txt| 39 ++
1 file changed, 39 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
diff --git
a/Documentation/devicetree/bindings/inte
Make it look like a real interrupt controller.
Signed-off-by: Marc Zyngier
---
.../devicetree/bindings/arm/omap/crossbar.txt | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
b/Documentation/d
Describe the legacy interrupt controller in every tegra DTSI files,
and make it the parent of most interrupts.
Signed-off-by: Marc Zyngier
---
arch/arm/boot/dts/tegra114.dtsi | 16 +++-
arch/arm/boot/dts/tegra124.dtsi | 16 +++-
arch/arm/boot/dts/tegra20.dtsi | 15 ++
The only user of the so called "routable domain" functionnality
now being fixed, let's clean up the GIC.
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic.c | 59 -
include/linux/irqchip/arm-gic.h | 6 -
2 files changed, 5 insertions(+), 6
Now that all DTs have been updated, entierely drop support for
the non-DT code.
This is likely to break platforms that do not update their DT,
so print a warning at boot time.
Signed-off-by: Marc Zyngier
---
arch/arm/mach-tegra/iomap.h | 15
arch/arm/mach-tegra/irq.c | 201 +
The gic_arch_extn hack that a number of platform use has been nagging
me for too long. It is only there for the benefit of a few platform,
and yet it impacts all GIC users. Moreover, it gives people the wrong
idea ("let's use it to put some new custom hack in there"...).
But now that stacked irq d
If we detect that our DT has a LIC node, don't setup gic_arch_extn,
and skip tegra_legacy_irq_syscore_init as well.
This is only a temporary measure until that code is removed for good.
Signed-off-by: Marc Zyngier
---
arch/arm/mach-tegra/irq.c | 11 +++
arch/arm/mach-tegra/tegra.c |
The GIC is now always initialized from DT on tegra, and there is
no point in keeping non-DT init code.
Signed-off-by: Marc Zyngier
---
arch/arm/mach-tegra/irq.c | 8
1 file changed, 8 deletions(-)
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index ab95f53..7f87a50
On 01/07/2015 05:30 AM, Marek Szyprowski wrote:
> This is an updated patchset, which intends to add support for L2 cache
> on Exynos4 SoCs on boards running under secure firmware, which requires
> certain initialization steps to be done with help of firmware, as
> selected registers are writable on
2015-01-06 5:25 GMT+09:00 Arnd Bergmann :
> On Monday 05 January 2015 13:19:00 Marek Szyprowski wrote:
>> DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
>> + .l2c_aux_val= OMAP_L2C_AUX_CTRL,
>> + .l2c_aux_mask = 0xcf9f,
>> + .l2c_write_sec = omap4_
On śro, 2015-01-07 at 13:56 +, Anand Moon wrote:
> Hi Kszysztof Kozlowski,
>
> I picked up the bellow line from
>
>
> Documentation/locking/lockdep-design.txt line no 18
>
> I understand that by enabling this flag we could detect possible
>
> deadlock situation with the kernel. Sorry fo
This patch enables hsotg and usbphy node to use USB 2.0 Device.
Signed-off-by: Jaewon Kim
---
arch/arm/boot/dts/exynos3250-rinato.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index 0e3d499
This patch adds device tree node for exynos_usbphy to use USB 2.0 Device.
Signed-off-by: Jaewon Kim
---
arch/arm/boot/dts/exynos3250.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 2246549..27d385
This patch adds device tree node for hsotg to control USB 2.0 Device.
Signed-off-by: Jaewon Kim
---
arch/arm/boot/dts/exynos3250.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 27d385f..204a84b 1
This patch adds device tree node for hsotg to control USB 2.0 Device.
Signed-off-by: Jaewon Kim
---
arch/arm/boot/dts/exynos3250-monk.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts
b/arch/arm/boot/dts/exynos3250-monk.dts
index 7102d88
This patch series adds USB device node and phy for exynos3250 SoC.
And enables for rinato and monk boards.
Changes in v2:
- remove unnessasary property "samsung,sysreg-phandle"
- change "xusbxti" clock to "CLK_SCLK_UPLL"
Jaewon Kim (4):
ARM: dts: Add exynos_usbphy node for exynos3250
ARM: d
This patch adds regulator-haptic device node controlled by regulator.
Signed-off-by: Jaewon Kim
Reviewed-by: Chanwoo Choi
---
arch/arm/boot/dts/exynos3250-monk.dts |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts
b/arch/arm/boot/dts/exynos3250
This patch series adds regulator-haptic device tree in rinato and monk boards.
The regulator-haptic has haptic motor and it is controlled by
voltage of regulator via force feedback framework.
Jaewon Kim (2):
ARM: dts: exynos3250-rinato: Add regulator-haptic node for haptics
ARM: dts: exynos32
This patch adds regulator-haptic device node controlled by regulator.
Signed-off-by: Jaewon Kim
Reviewed-by: Chanwoo Choi
---
arch/arm/boot/dts/exynos3250-rinato.dts |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos
On śro, 2015-01-07 at 18:29 +0530, Anand Moon wrote:
> Enable CONFIG_LOCKUP_DETECTOR to validate kernel locks state for exynos SOC.
>
> Enabling CONFIG_LOCKUP_DETECTOR help validator tracks the 'state' of
> lock-classes,
> and it tracks dependencies between different lock-classes.
> The validator
Hi Tony,
On 01/07/2015 01:08 PM, Tony K Nadackal wrote:
Dear Jacek,
On Wednesday, January 07, 2015 3:15 PM Jacek Anaszewski wrote,
Hi Tony,
Sorry for late response, just got back from vacation.
On 12/19/2014 04:37 AM, Tony K Nadackal wrote:
Hi Jacek,
On Wednesday, December 17, 2014 7:46 P
On śro, 2015-01-07 at 17:45 +0530, Anand Moon wrote:
> ARM Enable CONFIG_LOCKUP_DETECTOR to validation of kernel locks
>
> v2 Fixed the commit log
> This config item helps getting some useful information when lockup
> happens. If you want to validate locks then probably you want
> PROVE_LOCKING...
Hi Tony,
On 01/07/2015 12:22 PM, Tony K Nadackal wrote:
Hi Jacek,
On Wednesday, January 07, 2015 3:43 PM : Jacek Anaszewski wrote,
Hi Tony,
On 12/19/2014 08:38 AM, Tony K Nadackal wrote:
Fimp_jpeg used in Exynos7 is a revised version. Some register
configurations are slightly different fro
Dear Jacek,
On Wednesday, January 07, 2015 3:15 PM Jacek Anaszewski wrote,
> Hi Tony,
>
> Sorry for late response, just got back from vacation.
>
> On 12/19/2014 04:37 AM, Tony K Nadackal wrote:
> > Hi Jacek,
> >
> > On Wednesday, December 17, 2014 7:46 PM Jacek Anaszewski wrote,
> >> Hi Tony,
Hi Jacek,
On Wednesday, January 07, 2015 3:38 PM Jacek Anaszewski wrote,
> Hi Tony,
>
> On 12/19/2014 08:37 AM, Tony K Nadackal wrote:
> > Fix the bug in modifying the interrupt enable register.
>
> For Exynos4 this was not a bug as there are only five bit fields used in the
> EXYNOS4_INT_EN_RE
This patch implements generic DT L2C initialisation (the one from
init_IRQ in arch/arm/kernel/irq.c) for Omap4 and AM43 platforms and
kills the SoC specific stuff in arch/arm/mach-omap2/omap4-common.c.
Signed-off-by: Marek Szyprowski
Tested-by: Nishanth Menon
Acked-by: Nishanth Menon
Acked-by:
This is an updated patchset, which intends to add support for L2 cache
on Exynos4 SoCs on boards running under secure firmware, which requires
certain initialization steps to be done with help of firmware, as
selected registers are writable only from secure mode.
First patch updates Omap2+ platfor
From: Tomasz Figa
Certain platforms (i.e. Exynos) might need to set .write_sec callback
from firmware initialization which is happenning in .init_early callback
of machine descriptor. However current code will overwrite the pointer
with whatever is present in machine descriptor, even though it ca
From: Tomasz Figa
Certain implementations of secure hypervisors (namely the one found on
Samsung Exynos-based boards) do not provide access to individual L2C
registers. This makes the .write_sec()-based interface insufficient and
provoking ugly hacks.
This patch is first step to make the driver
From: Tomasz Figa
Because certain secure hypervisor do not allow writes to individual L2C
registers, but rather expect set of parameters to be passed as argument
to secure monitor calls, there is a need to provide an interface for the
L2C driver to ask the firmware to configure the hardware accor
All four register for latency and filter settings cannot be written in
non-secure mode and they should go through l2c_write_sec(). More on this
can be found in CoreLink Level 2 Cache Controller L2C-310 Technical
Reference Manual, 3.2. Register summary, table 3.1. This have been checked
the TRM for
From: Tomasz Figa
On Exynos SoCs it is necessary to resume operation of L2C early in
assembly code, because otherwise certain systems will crash. This patch
adds necessary code to non-secure resume handler.
Signed-off-by: Tomasz Figa
[rewrote the code accessing l2x0_saved_regs]
Signed-off-by: M
From: Tomasz Figa
Exynos4 SoCs equipped with an L2C-310 cache controller and running under
secure firmware require certain registers of aforementioned IP to be
accessed only from secure mode. This means that SMC calls are required
for certain register writes. To handle this, an implementation of
From: Tomasz Figa
Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
settings configured in registers leading to crashes if L2C is enabled
without overriding them. This patch introduces bindings to enable
prefetch settings to be specified from DT and necessary support in
From: Tomasz Figa
This patch adds device tree nodes for L2 cache controller present on
Exynos4 SoCs.
Signed-off-by: Tomasz Figa
Signed-off-by: Marek Szyprowski
Acked-by: Arnd Bergmann
Acked-by: Kukjin Kim
---
arch/arm/boot/dts/exynos4210.dtsi | 9 +
arch/arm/boot/dts/exynos4x12.dts
Hello,
On 2015-01-05 18:22, Nishanth Menon wrote:
On 13:19-20150105, Marek Szyprowski wrote:
From: Tomasz Figa
Certain implementations of secure hypervisors (namely the one found on
Samsung Exynos-based boards) do not provide access to individual L2C
registers. This makes the .write_sec()-bas
Hi Jacek,
On Wednesday, January 07, 2015 3:43 PM : Jacek Anaszewski wrote,
> Hi Tony,
>
> On 12/19/2014 08:38 AM, Tony K Nadackal wrote:
> > Fimp_jpeg used in Exynos7 is a revised version. Some register
> > configurations are slightly different from JPEG in Exynos4.
> > Added one more variant S
Hello,
On 2015-01-05 18:20, Nishanth Menon wrote:
On 13:19-20150105, Marek Szyprowski wrote:
All four register for latency and filter settings cannot be written in
non-secure mode and they should go through l2c_write_sec(). More on this
can be found in CoreLink Level 2 Cache Controller L2C-310
Hi Tony,
On 12/19/2014 08:38 AM, Tony K Nadackal wrote:
Fimp_jpeg used in Exynos7 is a revised version. Some register
configurations are slightly different from JPEG in Exynos4.
Added one more variant SJPEG_EXYNOS7 to handle these differences.
Signed-off-by: Tony K Nadackal
---
.../bindings/
Hi Tony,
On 12/19/2014 08:37 AM, Tony K Nadackal wrote:
Fix the bug in modifying the interrupt enable register.
For Exynos4 this was not a bug as there are only five bit fields
used in the EXYNOS4_INT_EN_REG - all of them enable related
interrupt signal and EXYNOS4_INT_EN_ALL value is 0x1f whi
Hi Javier,
On 01/07/2015 06:33 PM, Javier Martinez Canillas wrote:
> Hello Joonyoung,
>
> On 01/07/2015 03:03 AM, Joonyoung Shim wrote:
>> On 01/06/2015 06:49 PM, Javier Martinez Canillas wrote:
>>>
>>> Also I tried forcing the kernel to not disable unused power domains by
>>> passing the pd_igno
Add node for fuel gauge present in Maxim 77693 PMIC. This allows control
over battery charging state on Trats2 board.
The fuel gauge is compatible with max17042 battery driver (Maxim
17042/17047/17050). Although datasheet rev 2.2 for MAX77693 describes
fuel gauge as Maxim 17042-like, the chip on
Hi Tony,
Sorry for late response, just got back from vacation.
On 12/19/2014 04:37 AM, Tony K Nadackal wrote:
Hi Jacek,
On Wednesday, December 17, 2014 7:46 PM Jacek Anaszewski wrote,
Hi Tony,
Thanks for the patches.
Thanks for the review.
Please process them with scripts/checkpatch.pl
Hello Joonyoung,
On 01/07/2015 03:03 AM, Joonyoung Shim wrote:
> On 01/06/2015 06:49 PM, Javier Martinez Canillas wrote:
>>
>> Also I tried forcing the kernel to not disable unused power domains by
>> passing the pd_ignore_unused parameter to the kernel command line. I
>> see on the kernel log a
On wto, 2015-01-06 at 23:12 +0530, Anand Moon wrote:
> ARM Enable CONFIG_LOCKUP_DETECTOR to validaion of kernel locks
s/validaion/validation/
This config item helps getting some useful information when lockup
happens. If you want to validate locks then probably you want
PROVE_LOCKING... but its ov
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