Hello Sergei,
Thanks a lot for your feedback.
On 02/06/2015 08:09 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 02/06/2015 08:37 PM, Javier Martinez Canillas wrote:
>
>> All the device nodes for the Exynos5420 power-domains have a quite
>> generic "power-domain" name.
>
> And this is in confo
From: Gustavo Padovan
None of the exynos crtc drivers implements win_enable() so remove it for
better clarity of the code.
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/exynos/exynos_drm_drv.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h
b/
From: Gustavo Padovan
struct {fimd,mixer,vidi}_win_data was just keeping the same data
as struct exynos_drm_plane thus get ride of it and use exynos_drm_plane
directly.
It changes how planes are created and remove .win_mode_set() callback
that was only filling all *_win_data structs.
Signed-off
From: Gustavo Padovan
The .destroy() callback for exynos can be replaced by drm_plane_cleanup().
The only extra operation on exynos_plane_destroy() was a call to
exynos_plane_disable() but the plane is already disabled by a earlier call
to drm_framebuffer_remove().
Signed-off-by: Gustavo Padovan
From: Gustavo Padovan
Rip out the check from exynos_update_plane() and create
exynos_check_plane() for the check phase enabling use to use
the atomic helpers to call our check and update phases when updating
planes.
Update all users of exynos_update_plane() accordingly to call
exynos_check_plane
From: Gustavo Padovan
Set CRTC, planes and connectors to use the default implementations from
the atomic helper library. The helpers will work to keep track of state
for each DRM object.
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/bridge/ptn3460.c | 4
drivers/gpu/drm/
From: Gustavo Padovan
We already set each plane zpos at init, after that changes to zpos are
not expected. This patch turns zpos into a read-only property so now it is
impossible to set zpos.
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/exynos/exynos_drm_plane.c | 21 ++--
From: Gustavo Padovan
Usually userspace don't want to have two overlay planes on the same zpos
so this change assign a different zpos for each plane. Before this change
a zpos of value zero was created for all planes so the userspace had to
set up the zpos of every plane it wanted to use.
Also a
From: Gustavo Padovan
These functions were already removed by previous cleanup work, but these
ones were left behind.
Signed-off-by: Gustavo Padovan
Acked-by: Joonyoung Shim
---
drivers/gpu/drm/exynos/exynos_drm_crtc.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/e
From: Mandeep Singh Baines
The goal of the change is to make sure we send the vblank event on the
current vblank. My hope is to fix any races that might be causing flicker.
After this change I only see a flicker in the transition plymouth and
X11.
Simplified the code by tracking vblank events on
From: Gustavo Padovan
The new atomic infrastructure needs the .mode_set_nofb() callback to
update CRTC timings before setting any plane.
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 60 +---
1 file changed, 9 insertions(+), 51 deleti
From: Gustavo Padovan
Use drm_atomic_set_fb_for_plane() in the legacy page_flip path to keep
track of the framebuffer pointer and reference.
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/exynos
From: Gustavo Padovan
Hi,
This is the v2 of this patchset. The only difference here is that I added
the zpos refactor to this series after the review of v1 today. No changes
were made to atomic patches besides solving conflicts after the new zpos
changes.
This series clean ups a few more paths
From: Gustavo Padovan
Add CRTC callbacks .atomic_begin() .atomic_flush(). On exynos they
unprotect the windows before the commit and protects it after based on
a plane mask tha store which plane will be updated.
For that we create two new exynos_crtc callbacks: .win_protect() and
.win_unprotect(
From: Gustavo Padovan
It is not used outside of the plane scope anymore.
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/exynos/exynos_drm_plane.c | 11 ++-
drivers/gpu/drm/exynos/exynos_drm_plane.h | 5 -
2 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/drivers/
From: Gustavo Padovan
The atomic helper to disable planes also uses the optional
.atomic_disable() helper. The unique operation it does is calling
.win_disable()
exynos_drm_fb_get_buf_cnt() needs a fb check too to avoid a null pointer.
Signed-off-by: Gustavo Padovan
---
drivers/gpu/drm/exynos
Hello.
On 02/06/2015 08:37 PM, Javier Martinez Canillas wrote:
All the device nodes for the Exynos5420 power-domains have a quite
generic "power-domain" name.
And this is in conformance to the ePAPR standard.
So in case of an error, the Exynos PD
driver shows the following (not very usef
On Fri, Feb 06, 2015 at 05:59:07PM +0100, Lukasz Majewski wrote:
> This patch provides code for reading PWM FAN configuration data via
> device tree. The pwm-fan can work with full speed when configuration
> is not provided. However, errors are propagated when wrong DT bindings
> are found.
> Addit
On Fri, Feb 06, 2015 at 05:59:06PM +0100, Lukasz Majewski wrote:
> It was necessary to decouple code handling writing to sysfs from the one
> responsible for setting PWM of the fan.
> Due to that, new __set_pwm() method was extracted, which is responsible for
> only setting new PWM duty cycle.
>
>
From: Tushar Behera
On Snow, Peach Pit and Peach Pi boards, the Exynos SoC XCLKOUT output pin
provides the master clock (mclk) to codecs. So make them a clock consumer.
Signed-off-by: Tushar Behera
Signed-off-by: Javier Martinez Canillas
---
Changes since v1:
- Rebased on top of Kukjin's for
Many Exynos boards have an HDMI port so enable Exynos DRM HDMI support.
Signed-off-by: Javier Martinez Canillas
---
Exynos DRM HDMI has some issues that were fixed by Andrzej's [0] series.
So now is safe to HDMI support for Exynos boards.
[0]: https://lkml.org/lkml/2015/2/5/265
arch/arm/confi
All the device nodes for the Exynos5420 power-domains have a quite
generic "power-domain" name. So in case of an error, the Exynos PD
driver shows the following (not very useful) message:
"Power domain power-domain disable failed"
Use descriptive names to know on which PD enable or disable failed
Presented patches add support for Odroid's U3 optional CPU FAN, which uses PWM
subsystem for low level control.
After successful probe it registers itself as a cooling device for thermal
subsystem. To preserve the ability to use this fan as a PWM device stubs for
thermal_of_cooling_device_register
Odroid U3 fan can work without being registered as OF cooling device
(with CONFIG_THERMAL{_OF|} disabled).
In this situation it can be controlled via PWM entry at
/sys/class/hwmon/hwmon0/pwm1.
Therefore, the thermal_cdev_update() function needs a stub
to allow clean compilation.
Signed-off-by: Lu
The PWM FAN device can now be used as a thermal cooling device. Necessary
infrastructure has been added in this commit.
Signed-off-by: Lukasz Majewski
---
Changes for v2:
- Replace pwm_fan_cooling_states with pwm_fan_cooling_levels
- Update ctx->pwm_fan_state when correct data from device tree is
From: Kamil Debski
Add pwm-fan node to the Odroid-U3 board file to enable PWM control of the
cooling fan. In addition, add the "pwm" label to the pwm@139D node
in the exynos4412.dtsi.
Signed-off-by: Kamil Debski
[Rebased on the newest mainline by l.majew...@samsung.com]
---
Changes since v1
Odroid U3 fan can work without being registered as OF cooling device
(with CONFIG_THERMAL_OF disabled).
In this situation it can be controlled via PWM entry at
/sys/class/hwmon/hwmon0/pwm1.
Therefore, the thermal_of_cooling_device_register() function needs a stub
to allow clean compilation.
Signe
Explanation of several properties, which allow PWM fan working as a cooling
device, have been embraced in this commit.
Signed-off-by: Lukasz Majewski
---
Changes for v2:
- Rename cooling-pwm-values to cooling-levels
- Remove default-pulse-width property and stick to default hwmon policy
Changes f
With those bindings it is possible to use pwm-fan device available in
Odroid U3 as a cooling device.
Signed-off-by: Lukasz Majewski
---
Changes for v2:
- Rename cooling-pwm-values property to cooling-levels
Changes for v3:
- Change patch's topic to "ARM dts"
- Reduce maximal cooling-level to 230
It was necessary to decouple code handling writing to sysfs from the one
responsible for setting PWM of the fan.
Due to that, new __set_pwm() method was extracted, which is responsible for
only setting new PWM duty cycle.
Signed-off-by: Lukasz Majewski
---
Changes for v2:
- None
Changes for v3:
-
This patch provides code for reading PWM FAN configuration data via
device tree. The pwm-fan can work with full speed when configuration
is not provided. However, errors are propagated when wrong DT bindings
are found.
Additionally the struct pwm_fan_ctx has been extended.
Signed-off-by: Lukasz Ma
From: Tushar Behera
On Snow, Peach Pit and Peach Pi boards, the Exynos SoC XCLKOUT output pin
provides the master clock (mclk) to codecs. So make them a clock consumer.
Signed-off-by: Tushar Behera
Signed-off-by: Javier Martinez Canillas
---
arch/arm/boot/dts/exynos5250-snow.dts | 2 ++
This patch set adds the atlas clock hierarchy on Exynos7. It also
modifies the existing cpu clock infrastructure to handle exynos7
differences. These patches are a pre-requisite for enabling CPUFreq
on Exynos7.
This patch set has been tested on next-20150202 with samsung
clk tree (for-v3.20/clk/n
Add the Atlas CPU clock configuration data and instantiate the CPU clock
type for Exynos7.
Signed-off-by: Abhilash Kesavan
---
drivers/clk/samsung/clk-cpu.h |5 +
drivers/clk/samsung/clk-exynos7.c | 33 ++-
include/dt-bindings/clock/exynos7-c
Add clock support for the Atlas CPU block in Exynos7.
Signed-off-by: Abhilash Kesavan
---
.../devicetree/bindings/clock/exynos7-clock.txt|6 +
drivers/clk/samsung/clk-exynos7.c | 121
include/dt-bindings/clock/exynos7-clk.h| 20 +++-
3
The divider and mux register offsets and bits are different on
Exynos7 from the older SoCs. Add new pre/post rate change callbacks
for Exynos7 to handle these differences. To do this:
- Add a new exynos_cpuclk_soc_data structure that will hold
the SoC-specific pre/post rate change c
The exynos_tmu_data() function should on entrance test not only for valid
data pointer, but also for data->tmu_read one.
It is important, since afterwards it is dereferenced to get temperature code.
Signed-off-by: Lukasz Majewski
---
drivers/thermal/samsung/exynos_tmu.c | 2 +-
1 file changed, 1
Hi,
2015-02-06 Joonyoung Shim :
> Hi Gustavo,
>
> On 02/06/2015 02:59 AM, Gustavo Padovan wrote:
> > From: Gustavo Padovan
> >
> > struct {fimd,mixer,vidi}_win_data was just keeping the same data
> > as struct exynos_drm_plane thus get ride of it and use exynos_drm_plane
> > directly.
> >
> >
Hello,
On 2015-02-05 11:13, Carlo Caione wrote:
On Wed, Feb 4, 2015 at 11:21 AM, Marek Szyprowski
wrote:
On 2015-02-04 10:23, Carlo Caione wrote:
From: "Jasper St. Pierre"
Even without an iommu, NO_KERNEL_MAPPING is still convenient to save on
kernel address space in places where we don't n
On Fri, Feb 06, 2015 at 12:30:45PM +0100, Sylwester Nawrocki wrote:
> Thank you for merging it. I hope you picked up the previous 2 as well,
> I couldn't see them in your tree.
I probably will if I don't hear anything but since they don't need to go
as a bug fix I can leave Kukjin a bit longer t
On 05/02/15 20:41, Mark Brown wrote:
> On Tue, Feb 03, 2015 at 03:06:22PM +0100, Sylwester Nawrocki wrote:
>> I2S1, I2S2 on Exynos4 SoC series have limited functionality compared
>> to I2S0, "samsung,s3c6410-i2s" compatible should be used for them.
>
> I've applied this even though I really should
On Mon, Dec 08, 2014 at 10:16:37AM +0100, Richard Weinberger wrote:
> Am 08.12.2014 um 08:11 schrieb Julia Lawall:
> >>> diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c
> >>> index 35aef5e..0a9c41f 100644
> >>> --- a/drivers/mtd/nand/s3c2410.c
> >>> +++ b/drivers/mtd/nand/s3c24
Hello Andrzej,
On 02/06/2015 11:55 AM, Andrzej Hajda wrote:
> FIMD and MIXER IPs in disp1 power domain have async-bridges (to GSCALER),
> therefore their clocks should be enabled during power domain switch.
>
> Signed-off-by: Andrzej Hajda
> ---
> Hi,
>
> This is 2nd version of the patch. After
FIMD and MIXER IPs in disp1 power domain have async-bridges (to GSCALER),
therefore their clocks should be enabled during power domain switch.
Signed-off-by: Andrzej Hajda
---
Hi,
This is 2nd version of the patch. After decrypting manual and discussion
with Marek I guess this set of clocks is mo
Hello Joonyoung,
On 02/06/2015 06:27 AM, Joonyoung Shim wrote:
> On 02/05/2015 11:45 PM, Javier Martinez Canillas wrote:
>>
>> I also tested on an Exynos5420 Peach Pit Chromebook and both the "Power
>> domain power-domain disable failed" message and the system crash are gone.
>>
>
> Really gone
On Wed, Feb 04, 2015 at 11:31:42PM +0900, Kukjin Kim wrote:
> Hi,
>
> This is cpuidle update for v3.20.
> Please pull.
>
> Thanks,
> Kukjin
>
> The following changes since commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672:
>
> Linux 3.19-rc1 (2014-12-20 17:08:50 -0800)
>
> are available in the
On Wed, Feb 04, 2015 at 11:31:33PM +0900, Kukjin Kim wrote:
> Hi,
>
> Here is 4th DT updates for v3.20.
> Please pull.
>
> Note there are several dt updates in my tree which has a dependency with
> driver side for v3.20 and I hope it can be sent to upstream via arm-soc
> during late merge window.
On Wed, Feb 04, 2015 at 11:31:23PM +0900, Kukjin Kim wrote:
> Hi Arnd, Olof, Kevin
>
> Here is late pull request for exynos_defconfig updates for v3.20 and if
> you're OK please pull.
>
> Note this is based on previous exynos_defconfig pull-request during
> v3.19-rc.
>
> Thanks,
> Kukjin
>
>
>
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