Hello Krzysztof,
On 08/11/2015 04:15 AM, Krzysztof Kozlowski wrote:
With the latest patches the cpufreq-dt can be used on multiple
Exynos SoCs: 3250, 4210, 4212, 4412 and 5250.
Enable it along with default ondemand governor to conserve the energy,
reduce temperature while maintaining
On Mon, 03 Aug 2015, Krzysztof Kozlowski wrote:
On Odroid XU3 board (with S2MPS11 PMIC) the PWRHOLD bit in CTRL1
register must be manually set to 0 before initiating power off sequence.
One of usual power down methods for Exynos based devices looks like:
1. PWRHOLD pin of PMIC is connected
Hello Lee,
On Mon, Aug 10, 2015 at 6:13 PM, Lee Jones lee.jo...@linaro.org wrote:
On Mon, 10 Aug 2015, Lee Jones wrote:
On Fri, 07 Aug 2015, Javier Martinez Canillas wrote:
[snip]
Do you know what happened with this patches? I see 3/3 in linux-next
but no 1/3 and 2/3.
No idea why
Hi Shawn
On Thu, Aug 6, 2015 at 12:14 PM, Shawn Lin shawn@rock-chips.com wrote:
DesignWare MMC Controller can supports two types of DMA
mode: external dma and internal dma. We get a RK312x platform
integrated dw_mmc and ARM pl330 dma controller. This patch add
edmac ops to support these
On Fri, 07 Aug 2015, Javier Martinez Canillas wrote:
On Thu, Jun 25, 2015 at 2:20 AM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
This is a trivial series that do some changes to the dependency for the
ChromeOS EC drivers Kconfig symbols. The patches are on top of
Hi Thierry,
在 2015/8/10 21:17, Thierry Reding 写道:
On Mon, Aug 10, 2015 at 08:59:44PM +0800, Yakir Yang wrote:
Hi Thierry,
在 2015/8/10 18:00, Thierry Reding 写道:
On Sat, Aug 08, 2015 at 11:54:38AM +0800, Yakir Yang wrote:
[...]
edp: edp@ff97 {
[...]
On 11.08.2015 00:49, Lee Jones wrote:
On Mon, 03 Aug 2015, Krzysztof Kozlowski wrote:
On Odroid XU3 board (with S2MPS11 PMIC) the PWRHOLD bit in CTRL1
register must be manually set to 0 before initiating power off sequence.
One of usual power down methods for Exynos based devices looks
在 2015/8/11 2:03, Alim Akhtar 写道:
Hi Shawn
On Thu, Aug 6, 2015 at 12:14 PM, Shawn Lin shawn@rock-chips.com wrote:
DesignWare MMC Controller can supports two types of DMA
mode: external dma and internal dma. We get a RK312x platform
integrated dw_mmc and ARM pl330 dma controller. This patch
This patch add the uart2 devicetree node for Exynos3250 SoC.
Cc: Kukjin Kim kg...@kernel.org
Cc: Krzysztof Kozlowski k.kozlow...@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 7 +++
arch/arm/boot/dts/exynos3250.dtsi |
This patch add the MSHC2 (Mobile Storage Host Controller) devicetree node for
Exynos3250 SoC.
Cc: Kukjin Kim kg...@kernel.org
Cc: Krzysztof Kozlowski k.kozlow...@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 35
This patch add the UART2 / MMC2 devicetree node for Exynos3250 SoC and add
the related clocks (mux, divider, gate) of UART2 / MMC2 device.
Chanwoo Choi (4):
clk: samsung: exynos3250: Add UART2 clock
clk: samsung: exynos3250: Add MMC2 clock
ARM: dts: Add UART2 dt node for Exynos3250 SoC
This patch add the UART2 clocks (mux, divider, gate) of Exynos3250 SoC.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
drivers/clk/samsung/clk-exynos3250.c | 6 ++
With the latest patches the cpufreq-dt can be used on multiple
Exynos SoCs: 3250, 4210, 4212, 4412 and 5250.
Enable it along with default ondemand governor to conserve the energy,
reduce temperature while maintaining acceptable performance.
Signed-off-by: Krzysztof Kozlowski
On 10.08.2015 10:27, Kukjin Kim wrote:
Krzysztof Kozlowski wrote:
W dniu 08.08.2015 o 11:07, Viresh Kumar pisze:
On 08-08-15, 00:24, Rafael J. Wysocki wrote:
OK, so please let me know which patches you want me to pick up.
Ideally, I'd prefer them to be resent in a separate series with ACKs
Hi Inki,
2015-08-07 Inki Dae inki@samsung.com:
Hi Gustavo,
On 2015년 08월 06일 22:31, Gustavo Padovan wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
struct exynos_drm_encoder was justing wrapping struct drm_encoder, it had
only a drm_encoder member and the internal
Hi Thierry,
在 2015/8/10 18:00, Thierry Reding 写道:
On Sat, Aug 08, 2015 at 11:54:38AM +0800, Yakir Yang wrote:
[...]
edp: edp@ff97 {
[...]
hsync-active-high = 0;
vsync-active-high = 0;
interlaced = 0;
These look like they should
From: Viresh Kumar viresh.ku...@linaro.org
Migrate exynos_mct driver to the new 'set-state' interface provided by
clockevents core, the earlier 'set-mode' interface is marked obsolete
now.
This also enables us to implement callbacks for new states of clockevent
devices, for example:
On Sat, Aug 08, 2015 at 11:54:38AM +0800, Yakir Yang wrote:
[...]
edp: edp@ff97 {
[...]
hsync-active-high = 0;
vsync-active-high = 0;
interlaced = 0;
These look like they should come from the display mode definition (EDID)
rather
From: Alexey Klimov klimov.li...@gmail.com
Patch removes unneeded container_of() macro in exynos4_local_timer_setup().
Instead let's pass mevt pointer to setup and stop functions from
exynos4_mct_cpu_notify() and let them get evt pointer.
Tested on odroid-xu3.
Signed-off-by: Alexey Klimov
Hi Heiko,
在 2015/8/10 20:08, Heiko Stübner 写道:
Hi Yakir,
Am Samstag, 8. August 2015, 11:54:38 schrieb Yakir Yang:
+static int rockchip_dp_init(struct rockchip_dp_device *dp)
+{
+ struct device *dev = dp-dev;
+ struct device_node *np = dev-of_node;
+ int ret;
+
+ dp-grf
On Mon, Aug 10, 2015 at 08:59:44PM +0800, Yakir Yang wrote:
Hi Thierry,
在 2015/8/10 18:00, Thierry Reding 写道:
On Sat, Aug 08, 2015 at 11:54:38AM +0800, Yakir Yang wrote:
[...]
edp: edp@ff97 {
[...]
hsync-active-high = 0;
vsync-active-high =
Hi Yakir,
Am Samstag, 8. August 2015, 11:54:38 schrieb Yakir Yang:
+static int rockchip_dp_init(struct rockchip_dp_device *dp)
+{
+ struct device *dev = dp-dev;
+ struct device_node *np = dev-of_node;
+ int ret;
+
+ dp-grf = syscon_regmap_lookup_by_phandle(np, rockchip,grf);
+
22 matches
Mail list logo
