On Fri, Apr 11, 2014 at 11:10:59PM +0530, Srikanth Thokala wrote:
> I see this error too on my setup (Xilinx PCIe Root Complex Driver),
> https://lkml.org/lkml/2014/3/3/183
> After digging into it, I see I need to override the API
> pcibios_get_phb_of_node()
No, as I pointed out before, the DT n
On Mon, Apr 07, 2014 at 12:38:23PM -0400, Murali Karicheri wrote:
> On 3/25/2014 12:54 PM, Jason Gunthorpe wrote:
> >On Tue, Mar 25, 2014 at 08:44:36AM +0100, Arnd Bergmann wrote:
> >
> >>I have no idea how this would work with the standard interrupt-map property,
> &
On Tue, Mar 25, 2014 at 08:44:36AM +0100, Arnd Bergmann wrote:
> I have no idea how this would work with the standard interrupt-map property,
> since the legacy interrupt host is now the same device as the pci host.
>
> Maybe it's better to move the legacy irqchip handling entirely out of
> the d
On Thu, Mar 13, 2014 at 11:44:33AM -0600, Stephen Warren wrote:
> On 03/13/2014 11:40 AM, Tim Harvey wrote:
> > When using interrupt-maps, the size of a map entry is #address-cells +
> > #interrupt-cells for the parent interrupt controller. For the ARM GIC
> > address-cells should be 0 as this is
On Tue, Mar 04, 2014 at 06:54:24AM -0800, Tim Harvey wrote:
> When an interrupt-map contains multiple entries an imap pointer arithmetic
> bug can cause only the first entry to be properly evaluated and causes
> the out_irq parameters to be incorrect depending on the #interrupt-cells
> and #address
On Wed, Mar 05, 2014 at 02:25:51PM +0100, Lucas Stach wrote:
> - return pp->irq;
> + irq = of_irq_parse_and_map_pci(dev, slot, pin);
> + if (!irq)
> + irq = pp->irq;
In light of the two bugs that Tim found, it might be wise to throw a
'dev_warn(FW_BUG "Missing DT interrupt
On Mon, Mar 03, 2014 at 03:40:43PM -0800, Tim Harvey wrote:
> of_irq_parse_and_map_pci(). The GIC function that translates the
> interrupt per domain is given irq_data: 0x123 0x04 0x00
This has been shifted by 1 byte..
> IRQ 123, which should get 32 added to it for irq155). Instead, the
> imp
On Mon, Mar 03, 2014 at 09:49:52AM -0800, Tim Harvey wrote:
> I'm not clear why irq 20 is getting returned for all the slots with
> (slot%4)=0 and func=0. If I start debugging of_irq_parse_pci() I see
> that it walks up the tree until it gets to the pcie host controller
> then calls of_irq_parse_
On Fri, Feb 28, 2014 at 04:53:33PM -0800, Tim Harvey wrote:
> In testing this on IMX6 I'm finding that 'of_irq_parse_and_map_pci()'
> always returns -EINVAL because it can't find a dt node for the host
> bridge:
> http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/of/of_p
On Fri, Jun 07, 2013 at 01:59:43PM +0200, Arnd Bergmann wrote:
> On Friday 07 June 2013 18:19:40 Jingoo Han wrote:
> > Hi Jason Gunthorpe,
> >
> > I implemented 'Single domain' with Exynos PCIe for last two months;
> > however, it cannot work properly due to t
On Mon, Apr 08, 2013 at 06:08:53PM +0900, Jingoo Han wrote:
> I have a question. Now, I am reviewing the Tegra PCIe, Marvell PCIe
> patchset. However, in the case of Exynos PCIe, 'downstream I/O' and
> 'non-prefetchable memory' are different between PCIe0 and PCIe1.
> These regions are not share
On Wed, Mar 27, 2013 at 05:35:48PM +0900, Jingoo Han wrote:
> Here is the lspci -vv output.
> I tested Exynos PCIe with e1000e lan card.
>
> 00:00.0 PCI bridge: Samsung Electronics Co Ltd Device a549 (rev 01) (prog-if
> 00 [Normal decode])
> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWI
On Sat, Mar 23, 2013 at 01:09:18PM +0900, Jingoo Han wrote:
> + pcie0@4000 {
> + compatible = "samsung,exynos5440-pcie";
> + reg = <0x4000 0x4000
> + 0x29 0x1000
> + 0x27 0x1000
> + 0x271000 0x4
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