Hi Tomasz,
On 25/09/14 23:58, Tomasz Figa wrote:
On 10.09.2014 18:37, Sylwester Nawrocki wrote:
The default mux and divider clocks are specified in device tree
so that the FIMC devices in Exynos4210 and Exynos4x12 SoCs are
clocked from recommended clock source and with maximum supported
On 26.09.2014 13:01, Sylwester Nawrocki wrote:
Hi Tomasz,
On 25/09/14 23:58, Tomasz Figa wrote:
On 10.09.2014 18:37, Sylwester Nawrocki wrote:
The default mux and divider clocks are specified in device tree
so that the FIMC devices in Exynos4210 and Exynos4x12 SoCs are
clocked from
On 26/09/14 15:24, Tomasz Figa wrote:
I'm not concerned specifically with Exynos4210, but with placing such
kind of data in common dtsi files.
Notice that even on boards which have correct initialization done by
firmware, this will cause the settings to be overwritten, even if the
firmware
Hi Daniel,
On 18/09/14 21:27, Daniel Drake wrote:
On Wed, Sep 10, 2014 at 10:37 AM, Sylwester Nawrocki
s.nawro...@samsung.com wrote:
The default mux and divider clocks are specified in device tree
so that the FIMC devices in Exynos4210 and Exynos4x12 SoCs are
clocked from recommended
On 19/09/14 01:53, Daniel Drake wrote:
On Wed, Sep 10, 2014 at 10:37 AM, Sylwester Nawrocki
s.nawro...@samsung.com wrote:
The default mux and divider clocks are specified in device tree
so that the FIMC devices in Exynos4210 and Exynos4x12 SoCs are
clocked from recommended clock source and
On Thu, Sep 25, 2014 at 12:05 PM, Sylwester Nawrocki
s.nawro...@samsung.com wrote:
Just curious about the Exynos4x12 situation here.
You set the FIMC clocks as 176MHz, child of MPLL, which works for
ODROID with a divider:
880MHz MPLL / 5 = 176MHz
However, talking of recommended
On Thu, Sep 25, 2014 at 1:44 PM, Daniel Drake dr...@endlessm.com wrote:
AFAIK 880 MHz is recommended MPLL frequency for Exynos4412 EVT2.0, which
is revision of the Exynos4412 SoC the Odroid U3 boards are populated with.
You can read the main/sub revision information from the chip ID register
Hi Sylwester,
On 10.09.2014 18:37, Sylwester Nawrocki wrote:
The default mux and divider clocks are specified in device tree
so that the FIMC devices in Exynos4210 and Exynos4x12 SoCs are
clocked from recommended clock source and with maximum supported
frequency. If needed these settings
Hi Sylwester,
On Wed, Sep 10, 2014 at 10:37 AM, Sylwester Nawrocki
s.nawro...@samsung.com wrote:
The default mux and divider clocks are specified in device tree
so that the FIMC devices in Exynos4210 and Exynos4x12 SoCs are
clocked from recommended clock source and with maximum supported
On Wed, Sep 10, 2014 at 10:37 AM, Sylwester Nawrocki
s.nawro...@samsung.com wrote:
The default mux and divider clocks are specified in device tree
so that the FIMC devices in Exynos4210 and Exynos4x12 SoCs are
clocked from recommended clock source and with maximum supported
frequency. If
The default mux and divider clocks are specified in device tree
so that the FIMC devices in Exynos4210 and Exynos4x12 SoCs are
clocked from recommended clock source and with maximum supported
frequency. If needed these settings could be overrode in board
specific dts files, however they are in
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