Joonyoung Shim wrote:
>
> Add to cc Grant Likely and Linus Walleij
>
> On 05/18/2012 11:18 AM, Joonyoung Shim wrote:
> > Exynos4x12 GPIO part1 and part2 layouts are different with that of
> > Exynos4210. So, it needs to support gpios for Exynos4x12 SoC. This
> > doesn't support GPVx Exynos4x12 GP
On 05/18/2012 04:54 AM, Joonyoung Shim wrote:
> Add to cc Grant Likely and Linus Walleij
>
> On 05/18/2012 11:18 AM, Joonyoung Shim wrote:
>> Exynos4x12 GPIO part1 and part2 layouts are different with that of
>> Exynos4210. So, it needs to support gpios for Exynos4x12 SoC. This
>> doesn't support
Add to cc Grant Likely and Linus Walleij
On 05/18/2012 11:18 AM, Joonyoung Shim wrote:
Exynos4x12 GPIO part1 and part2 layouts are different with that of
Exynos4210. So, it needs to support gpios for Exynos4x12 SoC. This
doesn't support GPVx Exynos4x12 GPIO part4 yet.
In the Exynos4x12 GPIO par
Exynos4x12 GPIO part1 and part2 layouts are different with that of
Exynos4210. So, it needs to support gpios for Exynos4x12 SoC. This
doesn't support GPVx Exynos4x12 GPIO part4 yet.
In the Exynos4x12 GPIO part1 and part2, the interval of base register
offset is 0x20 but GPF0, GPJ0, GPK0 and GPM0 i
