Re: [PATCH 3/3] ARM: S5PC210: Set the common L2 cache configurations

On Tue, Sep 14, 2010 at 6:48 PM, Kukjin Kim wrote: > Kyungmin Park wrote: >> >> From: Kyungmin Park >> >> S5PC210 has PL310 1MiB L2 cache. >> It uses the optimized data & tag latency and also enable the prefetch. >> >> Signed-off-by: Kyungmin Park >> --- >>  arch/arm/mach-s5pv310/cpu.c |   19 ++

RE: [PATCH 3/3] ARM: S5PC210: Set the common L2 cache configurations

Kyungmin Park wrote: > > From: Kyungmin Park > > S5PC210 has PL310 1MiB L2 cache. > It uses the optimized data & tag latency and also enable the prefetch. > > Signed-off-by: Kyungmin Park > --- > arch/arm/mach-s5pv310/cpu.c | 19 +++ > 1 files changed, 19 insertions(+), 0 de