On 3 October 2013 02:37, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Vyacheslav, Tarek,
On Tuesday 01 of October 2013 20:17:06 Vyacheslav Tyrtov wrote:
From: Tarek Dakhran t.dakh...@samsung.com
Configure ARM_NR_BANKS as 16 for EXYNOS SoC.
Enable cci_control_port_by_index for ACE_PORT.
Add
Hi Vyacheslav, Tarek,
On Tuesday 01 of October 2013 20:17:06 Vyacheslav Tyrtov wrote:
From: Tarek Dakhran t.dakh...@samsung.com
Configure ARM_NR_BANKS as 16 for EXYNOS SoC.
Enable cci_control_port_by_index for ACE_PORT.
Add additional irqs for Exynos MCT.
Set irq base as 256 for EXYNOS5410
From: Tarek Dakhran t.dakh...@samsung.com
Configure ARM_NR_BANKS as 16 for EXYNOS SoC.
Enable cci_control_port_by_index for ACE_PORT.
Add additional irqs for Exynos MCT.
Set irq base as 256 for EXYNOS5410 SoC.
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
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arch/arm/Kconfig
Hi,
On Tuesday, October 01, 2013 08:17:06 PM Vyacheslav Tyrtov wrote:
From: Tarek Dakhran t.dakh...@samsung.com
Configure ARM_NR_BANKS as 16 for EXYNOS SoC.
Enable cci_control_port_by_index for ACE_PORT.
Add additional irqs for Exynos MCT.
Set irq base as 256 for EXYNOS5410 SoC.
It would