This serise is second part of [1] which was posted by Seungwon Jeon few months
back.
This adds HS400 mode support for exynos dw_mmc host controller.
Currently tested on Exynos5800-peach-pi platform and exynos7 platform for HS400
mode.
Appreciate testing on other exynos5 platform which supports
On Thu, Aug 28, 2014 at 2:48 AM, Mark Rutland wrote:
> Hi,
>
>> > + cpus {
>> > + #address-cells = <2>;
>> > + #size-cells = <0>;
>>
>> Why size-cells=2? Can you not fit a cpuid in 32 bits?
>
> As of commit 72aea393a2e7 (arm64: smp: honour #address-size when parsing
> CPU reg
On Thu, Aug 28, 2014 at 12:27 PM, Marc Zyngier wrote:
> On 28/08/14 18:03, Mark Rutland wrote:
>
>> From 67104ad5a56e4c18f9c41f06af028b7561740afd Mon Sep 17 00:00:00 2001
>> From: Mark Rutland
>> Date: Thu, 28 Aug 2014 17:41:03 +0100
>> Subject: [PATCH] Doc: dt: arch_timer: discourage clock-frequ
pport for of_earlycon
Probably you can re-spin this series without RFC tag and fixing a nit.
Please add command line support also and update the Documentation with
command line param.
> ARM: dts: exynos4: Add stdout-path properties
>
Have tested this on ARM64 based exynos7, both DT and comma
; drivers/tty/serial/Kconfig | 1 +
> drivers/tty/serial/samsung.c | 103
>
> 12 files changed, 129 insertions(+)
Tested this on ARM64 based exynos7 platform, both command line and DT
ways. Both works well.
Compile tes
Hi Tomasz,
On Tue, Sep 23, 2014 at 8:19 PM, Tomasz Figa wrote:
> On 23.09.2014 10:16, Abhilash Kesavan wrote:
> [snip]
>> @@ -383,9 +377,11 @@ static int exynos_wkup_irq_set_wake(struct irq_data
>> *irqd, unsigned int on)
>> /*
>> * irq_chip for wakeup interrupts
>> */
>> -static struct exy
CONFIG_SERIAL_SAMSUNG #ifdef in arch/arm/plat-samsung/init.c
Build tested using s3c2410_defconfig, s3c6400_defconfig, exynos_defconfig
and arm64's defconfig with and without the serial driver enabled. Boot tested
on Exynos5420 and Exynos7.
arch/arm/mach-s3c64xx/irq-pm.c |6 +++---
arch/arm
fconfig, exynos_defconfig
> and arm64's defconfig with and without the serial driver enabled. Boot tested
> on Exynos5420 and Exynos7.
>
> arch/arm/mach-s3c64xx/irq-pm.c |6 +++---
> arch/arm/plat-samsung/init.c |7 ++-
> 2 files changed, 5 insertions(+), 8 deletions
Hi Alim and Tomasz,
Thanks for the review.
On Wed, Oct 22, 2014 at 3:05 AM, Alim Akhtar wrote:
> Hi Tomasz,
>
> On Tue, Oct 21, 2014 at 7:30 PM, Tomasz Figa wrote:
>> On 21.10.2014 15:52, Alim Akhtar wrote:
+&mmc_0 {
+ status = "okay";
+ num-slots = <1>;
+
t;>>>> obj-$(CONFIG_PM_SLEEP) += suspend.o
>>>>> diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig
>>>>> index 2833b5b..f545d6c 100644
>>>>> --- a/drivers/soc/samsung/Kconfig
>>>>> +++ b/driver
exynos_pinctrl_resume,
+ }, {
+ /* pin-controller instance 9 data */
+ .pin_banks = exynos5433_pin_banks9,
+ .nr_banks = ARRAY_SIZE(exynos5433_pin_banks9),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend= exynos_pinct
eris: clock-controller@0x1004 {
>> +compatible = "samsung,exynos5433-cmu-peris";
>> +reg = <0x1004 0x0b20>;
>> +#clock-cells = <1>;
>> +};
>> +
>> +cmu_fsys: clock-controller@0x156e {
>&
5433_pin_banks8,
+ .nr_banks = ARRAY_SIZE(exynos5433_pin_banks8),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend= exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ }, {
+ /* pin-controller instance
e pin-controller.
- "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
+ - "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller.
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
- "samsu
3-gpio-ctrl8",
+ }, {
+ /* pin-controller instance 9 data */
+ .pin_banks = exynos5433_pin_banks9,
+ .nr_banks = ARRAY_SIZE(exynos5433_pin_banks9),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend= exynos_pi
suspend= exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ .label = "exynos5433-gpio-ctrl8",
+ }, {
+ /* pin-controller instance 9 data */
+ .pin_banks = exy
_gpio_init,
+ .suspend= exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ .label = "exynos5433-gpio-ctrl8",
+ }, {
+ /* pin-controller instance 9 data */
+ .pin_banks = exynos543
[#1] PREEMPT SMP
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.18.0-next-20141210+ #22
Hardware name: Samsung Exynos7 Espresso board based on EXYNOS7 (DT)
task: ffc00075e5c0 ti: ffc00074c000 task.ti: ffc00074c000
PC is at exynos4_jpeg_irq+0x30/0x15c
LR is at
On 07.09.2015 16:26, Alim Akhtar wrote:
> Hi Krzysztof,
>
> On 09/07/2015 11:03 AM, Krzysztof Kozlowski wrote:
>> On 04.09.2015 20:37, Alim Akhtar wrote:
>>> Corrects the CMU_TOPC block clock name as per user manual.
>>> This also adds few of the missing gate clocks of topc block.
>>> This does no
gt; > data, &exynos_sensor_ops);
> > if (IS_ERR(data->tzd)) {
> > pr_err("thermal: tz: %p ERROR\n", data->tzd);
> > return PTR_ERR(data->tzd);
> > }
> > - ret = exynos_map_dt_data(pdev);
> > - i
number of uart ports in
>> arch/arm/plat-samsung/init.c
>> - Removed CONFIG_SERIAL_SAMSUNG #ifdef in
>> arch/arm/plat-samsung/init.c
>>
>> Build tested using s3c2410_defconfig, s3c6400_defconfig, exynos_defconfig
>> and arm64's defconfig with and wi
refer to their parent clocks.
>>> Node of a device using power domains must have a samsung,power-domain
>>> property
>>> defined with a phandle to respective power domain.
>>> @@ -48,6 +49,7 @@ Example:
>>> mfc_pd: power-domain@10044060
Add assignment of the variant_regs field which is missing in commit
a5a56871f804edac93a53b5e871c0e9818fb9033 ("ASoC: samsung: add support
for exynos7 I2S controller"). Without this attempting to probe the
secondary DAI fails with an error like:
[1.763026] Unable to handle kernel NU
xynos4412-origen.dts | 1 +
>> arch/arm/boot/dts/exynos4412-smdk4412.dts | 1 +
>> arch/arm/boot/dts/exynos4412-tiny4412.dts | 4 +
>> arch/arm/boot/dts/exynos4412-trats2.dts | 1 +
>> drivers/tty/serial/Kconfig | 1 +
>>
nt_timer_delay(&exynos4_delay_timer);
>> +#endif
>
> Why not make both of these depend on CONFIG_ARM, rather than
> !CONFIG_ARM64? We care about the presence of the delay_timer struct and
> functions, which (from grepping around) exist in arch/arm and nowhere
> else.
You'
Add PMU settings for exynos7. This is required for future suspend-to-ram,
cpuidle and power domain support.
Note: In this patch some static declarations lines are over 80
characters per line for easy redability.
Reviewed-by: Pankaj Dubey
Signed-off-by: Eunseok Choi
Signed-off-by: Abhilash
tmu_intclear = EXYNOS5433_TMU_REG_INTPEND;
} else {
tmu_intstat = EXYNOS_TMU_REG_INTSTAT;
tmu_intclear = EXYNOS_TMU_REG_INTCLEAR;
@@ -926,6 +1062,7 @@ static const struct of_device_id exynos_tmu_match[] = {
{ .compatible = "samsung,exynos5260-tmu", },
rs/mmc/host/dw_mmc-exynos.c | 81
>> ++--
>> drivers/mmc/host/dw_mmc-exynos.h |1 +
>> 3 files changed, 67 insertions(+), 30 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.
rnal error: Oops: 9607 [#1] PREEMPT SMP Modules linked in:
> CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.18.0-next-20141210+ #22 Hardware
> name: Samsung Exynos7 Espresso board based on EXYNOS7 (DT)
> task: ffc00075e5c0 ti: ffc00074c000 task.ti: ffc00074c000 PC is at
> ex
it already
>>> available?
>> I am not sure what you have internally, any further suggestions on
>> this is most welcome.
>
> I believe Marek should be able to post our internal patch, so maybe you
> could reuse it and adapt for your needs.
>
>> As you said there
ain.
@@ -48,6 +49,7 @@ Example:
mfc_pd: power-domain@10044060 {
compatible = "samsung,exynos4210-pd", "samsung,exynos7-pd-mfc";
reg = <0x10044060 0x20>;
+ parents = <&pd_top>;
#power-domain-cells
Hi Mark,
On Thu, Aug 28, 2014 at 7:39 PM, Mark Rutland wrote:
>> >> Ok. If address-cells is kept at 2 the unit address needs to be changed
>> >> to "0,0". So one or the other has to be changed.
>> >
>> > I'm happy either way.
>> >
>> > I'm not sure the rest of the tree had "0," prefixes on all of
On Thu, Aug 28, 2014 at 06:33:13PM +0100, Rob Herring wrote:
> On Thu, Aug 28, 2014 at 12:27 PM, Marc Zyngier wrote:
> > On 28/08/14 18:03, Mark Rutland wrote:
> >
> >> From 67104ad5a56e4c18f9c41f06af028b7561740afd Mon Sep 17 00:00:00 2001
> >> From: Mark Rutland
> >> Date: Thu, 28 Aug 2014 17:41
On Thu, Aug 28, 2014 at 10:54 AM, Rob Herring wrote:
> On Thu, Aug 28, 2014 at 12:19 PM, Olof Johansson wrote:
>> On Thu, Aug 28, 2014 at 10:03 AM, Mark Rutland wrote:
>>> On Thu, Aug 28, 2014 at 05:28:22PM +0100, Olof Johansson wrote:
On Thu, Aug 28, 2014 at 2:48 AM, Mark Rutland wrote:
>
SoC specific patches to avoid large size of patch.
> With this approach there will not be unwanted big churns just after
> adding exynos-pmu under drivers/soc/samsung.
>
> All these patches are just refactoring to keep minimal changes while moving
> exynos-pmu driver under drivers/soc/sa
/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index ee4fc05..06455de 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -23,10 +23,6 @@ Required Properties:
- "samsung,
exynos-dw-mshc.txt
> b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
> index ee4fc05..06455de 100644
> --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
> +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
> @@ -23,10 +23,6 @@ Required Prope
s option if you want to use Exynos5433 DECON for DRM.
config DRM_EXYNOS7_DECON
bool "Exynos7 DRM DECON"
- depends on DRM_EXYNOS && !FB_S3C
+ depends on !FB_S3C
select FB_MODE_HELPERS
help
Choose this option if you want to use E
DECON-EXT.
>>> * DECON-EXT supports only H/w Triggered COMMAND mode.
>>> * DECON-EXT supports only one DMA window(window 1), so modify
>>> all window management routines to support 2 windows of DECON-INT
>>> and 1 window of DECON-EXT.
>>>
>>&
On Thu, Aug 28, 2014 at 06:47:00PM +0100, Geert Uytterhoeven wrote:
> Hi Mark,
>
> On Thu, Aug 28, 2014 at 7:39 PM, Mark Rutland wrote:
> >> >> Ok. If address-cells is kept at 2 the unit address needs to be changed
> >> >> to "0,0". So one or the other has to be changed.
> >> >
> >> > I'm happy e
The function exynos_irq_demux_eint16_31 uses pre-defined offsets for external
interrupt pending status and mask registers. So this function is not extensible
for Exynos7 SoC which has these registers at different offsets. Generalize
the exynos_irq_demux_eint16_31 function by using the pending/mask
The function exynos_irq_demux_eint16_31 uses pre-defined offsets for external
interrupt pending status and mask registers. So this function is not extensible
for Exynos7 SoC which has these registers at different offsets. Generalize
the exynos_irq_demux_eint16_31 function by using the pending/mask
Remove symbols SERIAL_SAMSUNG_UARTS_4 and SERIAL_SAMSUNG_UARTS which
select the number of UART ports available on the SoC. Replace the usage
of SERIAL_SAMSUNG_UARTS in the serial driver with the maximum number of
UART ports possible. Removal of these symbols also helps in Exynos7
serial enablement
The function exynos_irq_demux_eint16_31 uses pre-defined offsets for external
interrupt pending status and mask registers. So this function is not extensible
for Exynos7 SoC which has these registers at different offsets. Generalize
the exynos_irq_demux_eint16_31 function by using the pending/mask
these patches are just refactoring to keep minimal changes while moving
>> exynos-pmu driver under drivers/soc/samsung/. Support for exynos7 PMU can
>> be added on top of it, in such a manner that for ARM64 build, ARM related
>> SoC's PMU will not get compiled and thus unnecess
s/mmc/exynos-dw-mshc.txt
> +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
> @@ -23,10 +23,6 @@ Required Properties:
> - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
> specific extensions having an SMU.
>
> -* samsu
xt
>> b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> index ee4fc05..06455de 100644
>> --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> @@ -23,10 +23,6 @@ Required Properties:
&g
;;
Where the final cell is a sufficiently large value to cover all
addresses in the soc node.
[...]
> + gic:interrupt-controller@11001000 {
> + compatible = "arm,gic-400";
> + #interrupt-ce
Exynos7 SoC has now separate gate control for 125MHz pipe3 phy
clock, as well as 60MHz utmi phy clock.
So get the same and control in the phy-exynos5-usbdrd driver.
Signed-off-by: Vivek Gautam
---
.../devicetree/bindings/phy/samsung-phy.txt|4
drivers/phy/phy-exynos5-usbdrd.c
On 28/08/14 18:03, Mark Rutland wrote:
> From 67104ad5a56e4c18f9c41f06af028b7561740afd Mon Sep 17 00:00:00 2001
> From: Mark Rutland
> Date: Thu, 28 Aug 2014 17:41:03 +0100
> Subject: [PATCH] Doc: dt: arch_timer: discourage clock-frequency use
>
> The ARM Generic Timer (AKA the architected timer
ks that are useful for
> context save/restore for devices. Could you please describe in more
> detail which registers in which kind of devices need to be
> saved/restored, and why they cannot be saved/restored using existing
> mechanisms.
Basically the requirement is mandated by exyno
On Thu, Aug 28, 2014 at 06:27:04PM +0100, Marc Zyngier wrote:
> On 28/08/14 18:03, Mark Rutland wrote:
>
> > From 67104ad5a56e4c18f9c41f06af028b7561740afd Mon Sep 17 00:00:00 2001
> > From: Mark Rutland
> > Date: Thu, 28 Aug 2014 17:41:03 +0100
> > Subject: [PATCH] Doc: dt: arch_timer: discourage
arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -13,17 +13,17 @@ Required Properties:
Optional Properties:
- compatible: This is a second compatible name and gives the complete Power
- Domain name like "samsung,exynos7-pd-mfc".
-- clocks: L
NFIG_SERIAL_SAMSUNG_CONSOLE
and I do got below error [1]:
[1]:
drivers/built-in.o: In function `samsung_early_write':
/home/alim/linux-next/drivers/tty/serial/samsung.c:2442: undefined
reference to `uart_console_write'
make: *** [vmlinux] Error 1
and $SUBJECT patch does resolve [1],
So
_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_bus>;
+ status = "disabled";
+ };
+
+Example 3: SPI controller n
This series is based on exynos-drm-next branch of Inki Dae's tree at:
git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git
DECON(Display and Enhancement Controller) is the new IP
in exynos7 SOC for generating video signals using pixel data.
DECON driver can be used to dr
ping!
On Fri, Oct 10, 2014 at 6:18 PM, Ajay Kumar wrote:
> This series is based on exynos-drm-next branch of Inki Dae's tree at:
> git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git
>
> DECON(Display and Enhancement Controller) is the new IP
> in exynos
On Thu, Aug 28, 2014 at 03:23:49PM -0700, Olof Johansson wrote:
> On Thu, Aug 28, 2014 at 10:54 AM, Rob Herring wrote:
> > On Thu, Aug 28, 2014 at 12:19 PM, Olof Johansson wrote:
> >> On Thu, Aug 28, 2014 at 10:03 AM, Mark Rutland
> >> wrote:
> >>> On Thu, Aug 28, 2014 at 05:28:22PM +0100, Olof
s and code cleanups. The patches are based on top of current
exynos-drm-next branch.
Best regards
Marek Szyprowski
Samsung R&D Institute Poland
Patch summary:
Marek Szyprowski (17):
drm/exynos: rotator: convert to common clock framework
drm/exynos: exynos7-decon: remove excessive check
dr
SoC specific patches to avoid large size of patch.
> With this approach there will not be unwanted big churns just after
> adding exynos-pmu under drivers/soc/samsung.
>
> All these patches are just refactoring to keep minimal changes while moving
> exynos-pmu driver under drivers/soc/sa
approach there will not be unwanted big churns just after
adding exynos-pmu under drivers/soc/samsung.
All these patches are just refactoring to keep minimal changes while moving
exynos-pmu driver under drivers/soc/samsung/. Support for exynos7 PMU can
be added on top of it, in such a manner that for
While turning power domain to on/off, some clocks rates might change and
need to be saved/restored in the Exynos7 SOC. This patch adds the
framework for saving those clocks before power off and restoring it back
after power on operation.
Signed-off-by: Amit Daniel Kachhap
---
.../bindings/arm
approach there will not be unwanted big churns just after
adding exynos-pmu under drivers/soc/samsung.
All these patches are just refactoring to keep minimal changes while moving
exynos-pmu driver under drivers/soc/samsung/. Support for exynos7 PMU can
be added on top of it, in such a manner that for
these patches are just refactoring to keep minimal changes while moving
>> exynos-pmu driver under drivers/soc/samsung/. Support for exynos7 PMU can
>> be added on top of it, in such a manner that for ARM64 build, ARM related
>> SoC's PMU will not get compiled and thus u
15 pmic on exynos7-espresso board. Works well as before.
Fill free to add
Reviewed-by: Alim Akhtar
Tested-by: Alim Akhtar
---
Changes since v1:
1. None.
---
drivers/rtc/rtc-s5m.c | 40 +++-
1 file changed, 19 insertions(+), 21 deletions(-)
diff --git a/drive
ode that consumes the clock generated by the
> clock
> +controller.
> +
> + serial_0: serial@14C10000 {
> + compatible = "samsung,exynos5433-uart";
> + reg = <0x14C1 0x100>;
> + interrupts = <0 421 0>;
t are useful for
>> context save/restore for devices. Could you please describe in more
>> detail which registers in which kind of devices need to be
>> saved/restored, and why they cannot be saved/restored using existing
>> mechanisms.
>
> Basically the requirement is man
d I'm no longer
>> at Samsung; Marek might be able to take this topic), is it already
>> available?
> I am not sure what you have internally, any further suggestions on
> this is most welcome.
I believe Marek should be able to post our internal patch, so maybe you
could reus
This patch factors out the code that can be reused from
clk-exynos5260.c to clk-samsung/clk.c and clk-samsung/clk.h
As Clock controller in Exynos7 support various blocks in
CMU. The common functions and structures can be reused to
support Clock controller in Exynos7.
Signed-off-by: Naveen
Hello All,
On 27 August 2014 15:18, Naveen Krishna Chatradhi wrote:
> This patch factors out the code that can be reused from
> clk-exynos5260.c to clk-samsung/clk.c and clk-samsung/clk.h
>
> As Clock controller in Exynos7 support various blocks in
> CMU. The common functions and
error if connector driver like dsi or
>>>> dp was not probed. This is also not easy to me.
>>>
>>> In this case, if one of above gate clocks is enabled, the ACLK_200_DISP1
>>> should be enabled. So I guess the problem would be due to below line of
>>>
os_thermal_common.c
> delete mode 100644 drivers/thermal/samsung/exynos_thermal_common.h
> delete mode 100644 drivers/thermal/samsung/exynos_tmu_data.c
> create mode 100644 include/dt-bindings/thermal/thermal_exynos.h
Other than my earlier comments on the extra exynos_tmu_initialize()
and sysf
On Thu, Aug 28, 2014 at 05:28:22PM +0100, Olof Johansson wrote:
> On Thu, Aug 28, 2014 at 2:48 AM, Mark Rutland wrote:
> > Hi,
> >
> >> > + cpus {
> >> > + #address-cells = <2>;
> >> > + #size-cells = <0>;
> >>
> >> Why size-cells=2? Can you not fit a cpuid in 32 bits?
> >
>
>
>>> The runtime PM framework already provides callbacks that are useful for
>>> context save/restore for devices. Could you please describe in more
>>> detail which registers in which kind of devices need to be
>>> saved/restored, and why they cannot be saved/res
On Thu, Aug 28, 2014 at 10:03 AM, Mark Rutland wrote:
> On Thu, Aug 28, 2014 at 05:28:22PM +0100, Olof Johansson wrote:
>> On Thu, Aug 28, 2014 at 2:48 AM, Mark Rutland wrote:
>> > Hi,
>> >
>> >> > + cpus {
>> >> > + #address-cells = <2>;
>> >> > + #size-cells = <0>;
>> >>
>
for each operation
(read time, write time and alarm).
3. Splitting the configuration per S2MPS13, S2MPS14 and S2MPS15 thus
removing exceptions for them.
Signed-off-by: Krzysztof Kozlowski
Tested for s2mps15 pmic on exynos7-espresso board. rtc and timer works
as expected.
Fill free to
clock-names = "oscclk", "aclk_g3d_400";
+ clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
+ };
+
+ cmu_gscl: clock-controller@0x13cf {
+ compatible = "samsung,exynos5433-cmu-gscl";
+ reg = <0x1
"aclk_gscl_111",
>> +"aclk_gscl_333";
>> + clocks = <&xxti>,
>> +<&cmu_top CLK_ACLK_GSCL_111>,
>> +<&cmu_top CLK_ACLK_GSCL_333>;
&
hich registers in which kind of devices need to be
>>>> saved/restored, and why they cannot be saved/restored using existing
>>>> mechanisms.
>>>
>>> Basically the requirement is mandated by exynos7 manual. It tells that
>>> before turning off the po
On Thu, Aug 28, 2014 at 06:19:00PM +0100, Olof Johansson wrote:
> On Thu, Aug 28, 2014 at 10:03 AM, Mark Rutland wrote:
> > On Thu, Aug 28, 2014 at 05:28:22PM +0100, Olof Johansson wrote:
> >> On Thu, Aug 28, 2014 at 2:48 AM, Mark Rutland wrote:
> >> > Hi,
> >> >
> >> >> > + cpus {
> >> >> > +
: dts: exynos4: add rotator nodes
ARM: dts: exynos542x: add rotator node
drm/exynos: gsc: add device tree support and remove usage of static
mappings
drm/exynos: rotator: convert to common clock framework
drm/exynos: exynos7-decon: remove excessive check
drm/exynos: move dma_addr at
While turning power domain to on/off, some clocks need to be enabled
in the Exynos7 SOC. This patch adds the framework for enabling those
clocks before on/off and restoring it back after the operation. Also
these list of clocks may be different for on/off operation so not using
the generic pm
rties
>
>
> Patches have been prepared on top of linux-next from 10-11-2015. First
> 2 patches should be applied to Samsung SoC tree, all other should go
> to Exynos DRM tree.
>
> Best regards
> Marek Szyprowski
> Samsung R&D Institute Poland
>
>
> Patch summa
01c_, gic 1100_1000, serial0 14c1_, pinctrl 1058_
>> ...)
>> If we make the one dt node for clock domains like exynos4,
>> I think it may cause the possible issue that clock drivers may access
>> the un-related memory-mapped region.
>>
>> The
n_kms_drivers,
+ ARRAY_SIZE(exynos_drm_non_kms_drivers));
+}
+
static const char * const strings[] = {
"samsung,exynos3",
"samsung,exynos4",
@@ -593,19 +704,10 @@ static const char * const strings[] = {
on_kms_drivers(void)
> +{
> + return exynos_drm_register_drivers(exynos_drm_non_kms_drivers,
> + ARRAY_SIZE(exynos_drm_non_kms_drivers));
> +}
> +
> +static inline void exynos_drm_unregister_kms_drivers(void)
> +{
> + exynos_drm_unreg
fy i80 interface timing value,
+ it is not needed, but make it remain to use same kind of node
+ in fimd and exynos7 decon.
+
+Example:
+SoC specific DT entry:
+decon: decon@1380 {
+ compatible = "samsung,exynos5433-decon";
+ reg = <
p;cmu_peric CLK_PCLK_UART0>,
+<&cmu_peric CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_bus>;
+ status = "disabled&q
p;cmu_peric CLK_PCLK_UART0>,
+<&cmu_peric CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_bus>;
+
801 - 889 of 889 matches
Mail list logo
