Hello Jaehoon,
On Fri, Jan 23, 2015 at 3:23 PM, Jaehoon Chung jh80.ch...@samsung.com wrote:
Add sd0_rst node to exynos5420-pinctrl.dtsi.
(It's used on odroid-xu3 board)
It would be good to mention which device needs this pinctrl line.
Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com
---
system reboot procedure.
Patches looks good to me, I've only one comment on patch 1/3. Once
that is addressed, feel free to add for all the series:
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Best regards,
Javier
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Hello Marek,
On Mon, Feb 2, 2015 at 9:33 AM, Marek Szyprowski
m.szyprow...@samsung.com wrote:
+
+Required properties:
+- compatible : contains mmc-pwrseq-emmc.
+- reset-gpios : contains a GPIO specifier. The reset GPIO is pulled
The DT binding says that the reset-gpios is a required
Hello Marek,
On Fri, Dec 5, 2014 at 11:22 AM, Marek Szyprowski
m.szyprow...@samsung.com wrote:
On 2014-12-02 10:59, Sjoerd Simons wrote:
This is another attempt to finally make Exynos SYSMMU driver fully
integrated with DMA-mapping subsystem. The main change from previous
version is a rebase
Hello Krzysztof,
Hello Kukjin,
You dropped this patch since exynos drm was causing boot hangs on some
platforms but the fix for that issue is already in linux-next (commit:
f1e9203 clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable
failure due to domain being gated) so I think
Hello Kukjin,
Hello Kukjin,
Hi Javier,
Happy new year :)
Thanks, happy new year for you as well!
You dropped this patch since exynos drm was causing boot hangs on some
platforms but the fix for that issue is already in linux-next (commit:
f1e9203 clk: samsung: Fix Exynos 5420
Hello Kukjin,
On Mon, Jan 5, 2015 at 2:20 PM, Kukjin Kim kg...@kernel.org wrote:
Javier Martinez Canillas wrote:
I hope he can merge those patches as 3.19 fixes during the -rc cycle
to avoid having another kernel release with a non-working display on
Exynos5 boards.
Hi,
Hmm...Probably
Hello Hongbo,
On Mon, Jan 12, 2015 at 11:51 AM, Hongbo Zhang hongbo.zh...@linaro.org wrote:
On 9 January 2015 at 23:34, Javier Martinez Canillas
Yes, please take a look to Marek series [0]. Keep in mind that the
series does not support all sysmmu revisions so IOMMU is not supported
for some
Hello,
On 01/02/2015 02:32 PM, Javier Martinez Canillas wrote:
The mainline ChromeOS Embedded Controller (EC) driver is still missing some
features that are present in the downstream ChromiumOS tree. These are:
- Low Pin Count (LPC) interface
- User-space device interface
- Access
Hello Kukjin,
On 01/02/2015 04:24 PM, Javier Martinez Canillas wrote:
This series adds some DTS snippets that were missing in the mainline
Snow and Peach Pit/Pi Device Trees but are present in the downstream
ChromeOS kernel.
The series is composed of the following patches:
Javier
Hello Joonyoung,
On 01/12/2015 07:40 AM, Joonyoung Shim wrote:
And also making changes to the clocks in the clk-exynos5420 driver. Can
you please explain the rationale for those changes? I'm asking because
without your clock changes (only adding the DISP1 pd and making the
devices as
[adding Marek, Sjoerd and Joonyoung that were discussing about iommu
support in another thread]
Hello Hongbo,
On Fri, Jan 9, 2015 at 8:31 AM, Hongbo Zhang hongbo.zh...@linaro.org wrote:
Add linux-samsung-soc@vger.kernel.org mailing list.
On 7 January 2015 at 18:31, Hongbo Zhang
Hello Joonyoung,
On 01/07/2015 03:03 AM, Joonyoung Shim wrote:
On 01/06/2015 06:49 PM, Javier Martinez Canillas wrote:
Also I tried forcing the kernel to not disable unused power domains by
passing the pd_ignore_unused parameter to the kernel command line. I
see on the kernel log a genpd
On 01/14/2015 01:19 AM, Javier Martinez Canillas wrote:
I dug further on this issue and found that the cause is that the exynos_mixer
driver needs some clocks (CLK_HDMI and CLK_SCLK_HDMI) grabbed by exynos_hdmi
to be kept enabled after hdmi_poweroff (drivers/gpu/drm/exynos/exynos_hdmi.c
Hello Joonyoung,
On 01/13/2015 09:40 AM, Joonyoung Shim wrote:
These are the changes I have now [0]. Please let me know what you think.
Good, it's working with your patch without u-boot changes and reverting
of commit 2ed127697eb.
But i also get stripe hdmi output if hdmi/mixer
Hello Joonyoung,
On 01/13/2015 06:24 AM, Joonyoung Shim wrote:
Also, the SW_ACLK_300_DISP1 and USER_ACLK_300_DISP1 are needed for the FIMD
parent and input clock respectively. Adding those to the clocks list of the
DISP1 power domain gives me working display + HDMI on my Exynos5800 Peach Pi.
-by: Kevin Hilman khil...@kernel.org
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
It looks to me like a very nice cleanup.
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
and on an Exynos5800 Peach Pi Chromebook:
Tested-by: Javier Martinez Canillas javier.marti
not introduce any functional change except of visibility of
this domain to the system.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
Your patch looks good to me, I just have two small comments below. With
those changes, feel free to add:
Reviewed-by: Javier Martinez Canillas
Hello Stephen,
Thanks a lot for your feedback.
On 02/11/2015 07:54 PM, Stephen Boyd wrote:
On 02/11, Javier Martinez Canillas wrote:
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -799,7 +799,7 @@ clk_mux_determine_rate_flags(struct clk_hw *hw, unsigned
long rate
to change the assignments twice in all
the drivers, add a helper function to have an indirection level.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v1: None, new patch.
---
include/linux/clk-provider.h | 6 ++
1 file changed, 6 insertions(+)
diff --git
;
+ __clk_hw_set_clk(dst-hw, hw);
Fixes: 035a61c314eb3 (clk: Make clk API return per-user struct clk instances)
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v1:
- Don't only fix the case of composite clocks but in all the places where a
struct clk
Hello Stephen,
On 02/11/2015 07:50 PM, Stephen Boyd wrote:
---
Thanks for the patch.
Thanks a lot for your feedback.
Hello,
I set the rate and mux components' .core in clk_composite_determine_rate()
because that is the least intrusive change and where the .clk field is set
too but
that case.
Fixes: 035a61c314eb3 (clk: Make clk API return per-user struct clk instances)
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v2:
- Pass NULL struct clk_hw argument to __clk_determine_rate() if parent is NULL.
suggested by Stephen Boyd
] and this addresses issues pointed
out by Stephen Boyd.
This series is composed of the following patches:
Javier Martinez Canillas (3):
clk: Don't dereference parent clock if is NULL
clk: Add __clk_hw_set_clk helper function
clk: Replace explicit clk assignment with __clk_hw_set_clk
using the OF aliases approach that Sylwester suggested? But in any case
that could be complementary to your patch.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Suggested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Suggested-by: Sergei Shtylyov sergei.shtyl
Hello,
On 02/10/2015 01:30 PM, Krzysztof Kozlowski wrote:
On wto, 2015-02-10 at 15:21 +0300, Sergei Shtylyov wrote:
On 2/10/2015 3:17 PM, Krzysztof Kozlowski wrote:
Additionally (on Arndale Octa):
$ cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
domain
Hello Olof,
On 02/02/2015 12:26 PM, Javier Martinez Canillas wrote:
Hello,
The mainline ChromeOS Embedded Controller (EC) driver is still missing some
features that are present in the downstream ChromiumOS tree. These are:
- Low Pin Count (LPC) interface
- User-space device interface
+people involved in Exynos5420 S2R support (Abhilash, Vikas and Pankaj)
Hello Kevin,
On 03/17/2015 06:35 PM, Kevin Hilman wrote:
I've tried suspend/resume on peach-pi using v4.0-rc4, next/master and
samsung/for-next, and it doesn't seem to work on any of them.
The first problem was the
Hello Thomas,
On Tue, Feb 17, 2015 at 9:25 PM, Tobias Jakobi liquid.a...@gmx.net wrote:
Hello!
Lukasz Majewski wrote:
Hi Krzysztof, Thomas,
2015-01-08 22:17 GMT+01:00 Kevin Hilman khil...@kernel.org:
Hi Thomas,
Do you plan to continue with this work? It would be very helpful.
+1 from
Hello Alim,
On Wed, Mar 18, 2015 at 4:08 AM, Alim Akhtar alim.akh...@samsung.com wrote:
From: Seungwon Jeon tgih@samsung.com
HS400 timing values are added for SMDK5420, exynos5420-peach-pit
and exynos5800-peach-pi boards.
This also adds RCLK GPIO line, this gpio should be in pull-down
Hello Tobias,
On 03/18/2015 02:00 PM, Tobias Jakobi wrote:
Hello Javier,
I noticed that this recent commit breaks rtc-s3c on my Odroid-X2
(Exynos4412). The exynos4 dtsi includes a rtc of type s3c6410. Hence all
board files based on exynos4, and using the rtc-s3c, are now required to
Hello Andreas,
index f02775487cd4..b9ec763a5602 100644
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -25,6 +25,7 @@
chosen {
bootargs = console=tty1;
+ stdout-path = serial3:115200n8;
Is this a guess or did
Hello Andreas,
On Mon, Mar 16, 2015 at 11:27 AM, Andreas Färber afaer...@suse.de wrote:
Am 16.03.2015 um 08:56 schrieb Javier Martinez Canillas:
I think this should be defined in exynos5410.dtsi instead since is an
IP block in the SoC and referenced in the .dts using a label to change
Hello,
On 03/16/2015 01:15 PM, Andreas Färber wrote:
Am 14.03.2015 um 09:11 schrieb Javier Martinez Canillas:
By making the DP controller a consumer of DISP1, the PD is powered
off when the exynos-dp probe is deferred and powered on again when
the exynos-drm driver is probed
Hello,
On 03/16/2015 03:16 PM, Javier Martinez Canillas wrote:
Tested-by: Andreas Färber afaer...@suse.de
This fixes the display on the Spring Chromebook as well!
Thanks for testing Andreas but this patch seems to only solve a symptom
rather than the root cause.
Since the error
Hello Kukjin,
On Fri, Feb 6, 2015 at 6:42 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Many Exynos boards have an HDMI port so enable Exynos DRM HDMI support.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Exynos DRM HDMI has some issues
the behaviour is as expected on
disable.
Signed-off-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk
The patch looks good to me.
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Best regards,
Javier
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the XrtcXTI source clock (32.768kHz). Looks good to me.
Reviewed-by: Chanwoo Choi cw00.c...@samsung.com
Yes, I also think this is the correct fix for these boards.
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Thanks,
Chanwoo Choi
Best regards,
Javier
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Hello,
On 03/13/2015 12:38 PM, Javier Martinez Canillas wrote:
Exynos serial ports operate either in a DMA-based or interrupt-based
modes. In DMA-based mode, the UART generates a transfer data request
and a Transmission (Tx) interrupt in interrupt-based mode.
The Tx IRQ is only unmasked
Hello Abhilash,
On 03/20/2015 06:40 PM, Abhilash Kesavan wrote:
I have made some progress on this. This is the current state:
If I use next-20141114 (which was when the S2R code first appeared in
linux-next), then all is good. next-20141117 is fine too but things
are broken in
Hello Abhilash,
On 03/20/2015 03:23 PM, Abhilash Kesavan wrote:
On 03/17/2015 06:35 PM, Kevin Hilman wrote:
Anyone else having better luck with suspend/resume on peach-pi?
# echo +2 /sys/class/rtc/rtc0/wakealarm echo mem /sys/power/state
Suspend and CPUs shutdown seems to succeed
---
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Best regards,
Javier
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-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Best regards,
Javier
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The kernel can use as the default console a serial port if is defined
as stdout device in the Device Tree.
This allows a board to be booted without the need of having a console
parameter in the kernel command line.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
arch
users that don't have a serial console on this board might
be using it to have the boot log shown in the display. This will have
more precedence than the stdout-path but it's fine since is only used
when CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is enabled.
Signed-off-by: Javier Martinez Canillas
and
is composed of the following patches:
Javier Martinez Canillas (3):
ARM: dts: Define stdout-path property for Peach boards
ARM: dts: Define stdout-path property for Snow board
ARM: dts: Define stdout-path property for Spring board
arch/arm/boot/dts/exynos5250-snow.dts | 1 +
arch/arm/boot
users that don't have a serial console on this board might
be using it to have the boot log shown in the display. This will have
more precedence than the stdout-path but it's fine since is only used
when CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is enabled.
Signed-off-by: Javier Martinez Canillas
the node name but for
example in pinctrl lines we were sorting using the GPIO bank and
offset so if we want to use the same policy here, this should be
green, blue and red.
Either way is good to me though so is up to you.
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Best
Hello Inki,
On 03/10/2015 03:50 AM, Inki Dae wrote:
On 2015년 03월 07일 00:07, Javier Martinez Canillas wrote:
Another thing that may be useful to detect these issues early is to have
exynos-drm-next be pulled by linux-next since otherwise the integration
is not tested until the changes
Hello Kukjin,
On 02/05/2015 03:45 PM, Javier Martinez Canillas wrote:
Hello Andrzej,
Thanks a lot for finally finding what was causing the HDMI issue.
On 02/05/2015 01:35 PM, Andrzej Hajda wrote:
Hi,
Exynos chipsets since 542x have asynchronous bridges connecting different
IPs
Hello Inki,
On 03/06/2015 02:32 PM, Inki Dae wrote:
Another interesting data point is that the error in next-20150303 for
these 2 boards was the NULL pointer dereference in exynos_plane_destroy
that I got with 4.0-rc2 (when IOMMU is disabled) in Snow and Peach Pit.
I think the NULL
Hello Kukjin,
On Fri, Mar 6, 2015 at 10:43 AM, Kukjin Kim kg...@kernel.org wrote:
Javier Martinez Canillas wrote:
Hello Arnd,
Hi,
On Thu, Mar 5, 2015 at 12:04 AM, Arnd Bergmann a...@arndb.de wrote:
On Wednesday 04 March 2015 21:04:40 Arnd Bergmann wrote:
On Tuesday 03 March 2015 04:00
Exynos Chromebooks have an Embedded Controller known as the ChromeOS EC
Enable the driver that provides an interface to access from user-space.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
arch/arm/configs/exynos_defconfig | 2 ++
1 file changed, 2 insertions
.
This patch fixes video display on an Exynos5250 Snow Chromebook.
Fixes: 2d2c9a8d0a4f (ARM: dts: add display power domain for exynos5250)
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Hello Andrzej and Marek,
I need this patch to have display working on an Snow
Hello Kukjin,
On Fri, Mar 6, 2015 at 10:43 AM, Kukjin Kim kg...@kernel.org wrote:
Yes, the problem is the Exynos DRM driver which has a lot of issues.
It's broken if CONFIG_DRM_EXYNOS_IOMMU is enabled which defaults to
yes after commit 8dcc14f82f06 (drm/exynos: IOMMU support should not
be
-by: Puthikorn Voravootivat put...@chromium.org
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/mfd/cros_ec_i2c.c | 1 -
drivers/mfd/cros_ec_spi.c | 1 -
drivers/platform/chrome/cros_ec_lpc.c | 1 -
include/linux/mfd/cros_ec.h | 2 --
4
EC in a system
Javier Martinez Canillas (2):
mfd: cros_ec: Sanity check in and out sizes
platform/chrome: cros_ec_lpc - Use existing function to check EC
result
Stephen Barber (3):
mfd: cros_ec: rev cros_ec_commands.h
mfd: cros_ec: add proto v3 skeleton
mfd: cros_ec: add bus
...@oracle.com
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/mfd/cros_ec.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/mfd/cros_ec.c b/drivers/mfd/cros_ec.c
index c4aecc6f8373..07c53c27c82a 100644
--- a/drivers/mfd/cros_ec.c
+++ b
rspang...@chromium.org
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/platform/chrome/cros_ec_lightbar.c | 14 +-
include/linux/mfd/cros_ec_commands.h | 277 ++---
2 files changed, 262 insertions(+), 29 deletions(-)
diff --git
...@chromium.org
Reviewed-by: Dmitry Torokhov d...@chromium.org
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/mfd/cros_ec.c | 7 ++-
drivers/platform/chrome/cros_ec_dev.c | 4 ++--
include/linux/mfd/cros_ec.h | 2 ++
3 files changed
...@chromium.org
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/mfd/cros_ec_i2c.c | 166 +-
drivers/mfd/cros_ec_spi.c | 395 +-
drivers/platform/chrome/cros_ec_lpc.c | 73 ++-
include/linux/mfd
From: Todd Broch tbr...@chromium.org
If the EC device tree node has sub-nodes, try to instantiate them as
MFD sub-devices. We can configure the EC features provided by the board.
Signed-off-by: Todd Broch tbr...@chromium.org
Signed-off-by: Javier Martinez Canillas javier.marti
for handling proto v3 packets.
Signed-off-by: Stephen Barber smbar...@chromium.org
Reviewed-by: Puthikorn Voravootivat put...@chromium.org
Reviewed-by: Gwendal Grignou gwen...@chromium.org
Tested-by: Puthikorn Voravootivat put...@chromium.org
Signed-off-by: Javier Martinez Canillas javier.marti
Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/platform/chrome/cros_ec_lpc.c | 14 ++
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/drivers/platform/chrome/cros_ec_lpc.c
b/drivers/platform/chrome/cros_ec_lpc.c
index 860310513cf0..3a675817c95d 100644
interrupt enabling)
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
I noticed this issue on an Exynos5250 Snow, Exynos5420 Peach Pit and Exynos
5800 Peach Pi Chromebooks. This patch fixes the issue on all of them.
The offending commit landed in v4.0-rc1 so this fix is -rc
Hello Kukjin,
On Tue, Mar 17, 2015 at 7:54 PM, Javier Martinez Canillas
jav...@dowhile0.org wrote:
On Fri, Feb 6, 2015 at 6:42 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Many Exynos boards have an HDMI port so enable Exynos DRM HDMI support.
Signed-off-by: Javier
This patch enables the needed options to mount a rootfs over
NFS and also the needed support for automatic configuration
of IP addresses during boot as needed by NFS.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
arch/arm/configs/exynos_defconfig | 6 ++
1 file
This patch enables the options to mount a rootfs over NFS and also support
for automatic configuration of IP addresses during boot as needed by NFS.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v1:
- Found a typo in the changelog after posting
as
an index so it has a linear search time.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/clk/samsung/clk.c | 6 ++
drivers/clk/samsung/clk.h | 3 +++
2 files changed, 9 insertions(+)
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
suspend
and resume callbacks [0] and a re-spin [1] but was asked by Abhilash and
Chanwoo to do it in the clock driver instead.
So this series is an attempt to fix the issue and is composed of patches:
Javier Martinez Canillas (2):
clk: samsung: Add a clock lookup function
clk: exynos5420: Make
, rtc_src;
+};
Exynos's RTC must need the XrtcXTI source clock (32.768kHz). Looks good to me.
Reviewed-by: Chanwoo Choi cw00.c...@samsung.com
Thanks,
Chanwoo Choi
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Best regards,
Javier
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Choi cw00.c...@samsung.com
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Best regards,
Javier
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...@samsung.com
Thanks,
Chanwoo Choi
--
Looks good to me also.
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Best regards,
Javier
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More majordomo
k.kozlow...@samsung.com
Acked-by: Alexandre Belloni alexandre.bell...@free-electrons.com
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Best regards,
Javier
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it in the exynos5420 clk driver instead but maybe you
have a different opinion on that.
Best regards,
Javier
[0]:
From c118df83da8cac65cc218ae944362259f5d0 Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas javier.marti...@collabora.co.uk
Date: Mon, 30 Mar 2015 17:11:40 +0200
Subject: [RFC] clk
runtime Power Management
support v12)
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/clk/samsung/clk-exynos5420.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk
Hello Chanwoo,
Thanks a lot for your feedback.
On 03/30/2015 04:04 AM, Chanwoo Choi wrote:
I faced on the similiar issue. If some clock was disabled,
Exynos SoC could not enter the suspend mode
But, I think it is not prpper method to resolve this issue.
about that that specific clock
Hello Tomasz,
On 03/30/2015 06:02 PM, Tomasz Figa wrote:
Hi Javier,
2015-03-31 0:53 GMT+09:00 Javier Martinez Canillas
javier.marti...@collabora.co.uk:
The Samsung helpers functions to register clocks, add the clock instance
returned by the common clock framework to a lookup table
Hello Tomasz,
Thanks a lot for your feedback.
On 03/30/2015 06:07 PM, Tomasz Figa wrote:
Hi Javier,
Please see my comments inline.
2015-03-31 0:53 GMT+09:00 Javier Martinez Canillas
javier.marti...@collabora.co.uk:
[snip]
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers
Hello Markus,
On 03/31/2015 01:48 PM, Markus Reichl wrote:
The Exynos5422 SoC has a s3c6410 RTC where the source clock
is now a mandatory property.
This patch fixes probe failure of s3c-rtc on Odroid-XU3 boards.
It is based on v4.0-rc2.
---
Changes since v3:
1. Readded slipped #include
Hello Mike,
On 04/01/2015 03:29 AM, Michael Turquette wrote:
Quoting Javier Martinez Canillas (2015-03-31 01:59:39)
+Tomeu who I forgot to add to the cc list.
Hello Mike,
Thanks a lot for your feedback.
On 03/31/2015 03:40 AM, Michael Turquette wrote:
I don't performance is a big
Hello Sylwester,
On 04/01/2015 01:03 PM, Sylwester Nawrocki wrote:
On 31/03/15 22:00, Javier Martinez Canillas wrote:
On 03/31/2015 04:38 PM, Abhilash Kesavan wrote:
javier.marti...@collabora.co.uk wrote:
Unfortunately I don't fully understand why this clock needs to be
enabled. It would
Hello Inki,
On Fri, Mar 27, 2015 at 2:47 AM, Inki Dae inki@samsung.com wrote:
Right, this is not documented but if you have ever checked exynos drm
driver tree, then I think you could know how we use the prefix. Of
course, I don't like to force the use of this prefix but if you and
other
Hello Abhilash,
On 03/20/2015 06:40 PM, Abhilash Kesavan wrote:
Regarding the mdma0 disablement, it looks like for the system to
suspend properly the mdma0 pclk needs to stay on.
I had time today again to work on this issue and the best
place I found to enable and disable the mdma0 clock
runtime Power Management
support v12)
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
arch/arm/mach-exynos/suspend.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 1521eaf99265
:
Javier Martinez Canillas (2):
clk: exynos5420: Add alias for MDMA0 controller clock
ARM: EXYNOS: Make sure that the Exynos5420 MDMA0 clock is enabled
during suspend
arch/arm/mach-exynos/suspend.c | 15 +++
drivers/clk/samsung/clk-exynos5420.c | 2 +-
2 files changed, 16
Hello Abhilash,
On 03/27/2015 03:06 PM, Abhilash Kesavan wrote:
Hello Javier,
On Fri, Mar 27, 2015 at 6:59 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Abhilash,
On 03/20/2015 06:40 PM, Abhilash Kesavan wrote:
Regarding the mdma0 disablement, it looks like
enabled during suspend, an alias has to be added so a clock
lookup for a clock is registered.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/clk/samsung/clk-exynos5420.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk
Hello Krzysztof,
On 03/27/2015 03:29 PM, Krzysztof Kozlowski wrote:
2015-03-23 11:49 GMT+01:00 Javier Martinez Canillas
I looked at the DP and FIMD drivers and with great help of Andrzej
Hajda found the issue: the FIMD driver does not enable DP clock
(DP_MIE_CLKCON register). The process
Hello Sylwester,
Thanks a lot for your feedback.
On 03/27/2015 03:36 PM, Sylwester Nawrocki wrote:
* GIC wake-up support
@@ -374,6 +376,16 @@ static void exynos5420_pm_prepare(void)
{
unsigned int tmp;
+/*
+ * Exynos5420 requires the MDMA0 controller clock to be
+ *
Hello Abhilash,
On 03/31/2015 04:38 PM, Abhilash Kesavan wrote:
javier.marti...@collabora.co.uk wrote:
On 03/30/2015 06:07 PM, Tomasz Figa wrote:
If look-up speed is important here, maybe all the relevant clocks
could be looked up once at initialization time and just prepared and
off when not needed which is
better in terms of power consumption but for now is safer to just
revert the commit to avoid adding a regression in some machines.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
arch/arm/boot/dts/exynos5250.dtsi | 10 --
1 file
Hello Kukjin,
On 03/02/2015 08:43 PM, Kukjin Kim wrote:
On 02/27/15 15:20, Javier Martinez Canillas wrote:
Hello Kukjin,
Hi,
On 02/17/2015 12:38 PM, Javier Martinez Canillas wrote:
Can you please pick this patch? linux-next is still broken for many Exynos
boards after commit
Hello Kukjin,
On 02/06/2015 12:27 PM, Javier Martinez Canillas wrote:
Hello Andrzej,
On 02/06/2015 11:55 AM, Andrzej Hajda wrote:
FIMD and MIXER IPs in disp1 power domain have async-bridges (to GSCALER),
therefore their clocks should be enabled during power domain switch.
Signed-off
.
Signed-off-by: Arnd Bergmann a...@arndb.de
The patch looks good to me.
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Best regards,
Javier
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Hello,
On 02/27/2015 01:11 AM, Olof Johansson wrote:
On Thu, Feb 26, 2015 at 3:35 PM, Gwendal Grignou gwen...@chromium.org wrote:
Tested-by: Gwendal Grignou gwen...@chromium.org
Reviewed-by: Gwendal Grignou gwen...@chromium.org
Tested on a chromebook pixel with kernel 4.0.0-rc1 and ectool
Hello Kukjin,
On 02/17/2015 12:38 PM, Javier Martinez Canillas wrote:
Enabling Exynos DRM IOMMU support for Exynos is currently broken and
causes a BUG on exynos-iommu driver. This was not an issue since the
options was disabled in exynos_defconfig but after commit 8dcc14f82f06
(drm/exynos
Hello Arnd,
On Thu, Mar 5, 2015 at 12:04 AM, Arnd Bergmann a...@arndb.de wrote:
On Wednesday 04 March 2015 21:04:40 Arnd Bergmann wrote:
On Tuesday 03 March 2015 04:00:14 Kukjin Kim wrote:
Please pull Samsung tmu and hdmi regression fixes for v4.0 and I know
this is quite big for fixes but
+Gustavo which has been looking at the issues
Hello,
On 03/04/2015 09:50 AM, Marek Szyprowski wrote:
Hello,
On 2015-03-03 21:36, Kevin Hilman wrote:
Javier Martinez Canillas javier.marti...@collabora.co.uk writes:
Enabling Exynos DRM IOMMU support for Exynos is currently broken
Hello Marek,
Patch looks good to me. Just a small comment below so feel free to add my
Reviewed by: Javier Martinez Canillas javier.marti...@collabora.co.uk
On Thu, Mar 5, 2015 at 1:28 PM, Marek Szyprowski
m.szyprow...@samsung.com wrote:
This patch adds nodes for hardware JPEG codec found
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