Hi Rob,
On 10/31/2015 12:46 AM, Rob Herring wrote:
On Wed, Oct 28, 2015 at 3:28 AM, Yakir Yang <y...@rock-chips.com> wrote:
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Reviewed-by: Heiko St
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Reviewed-by: Heiko Stuebner <he...@sntech.de>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v10:
- Removed the duplicated signed-
Hi Brain,
On 11/03/2015 12:38 PM, Brian Norris wrote:
Hi Yakir,
On Thu, Oct 29, 2015 at 09:58:38AM +0800, Yakir Yang wrote:
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner<he...@sntech
Hi all,
Friendly ping. :)
Best regards,
- Yakir
On 09/22/2015 03:20 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288
Hi Javier,
On 10/07/2015 04:46 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/07/2015 08:25 AM, Yakir Yang wrote:
Hi all,
Friendly ping. :)
Best regards,
- Yakir
Do you have a tree that I can use to test these patches?
Wow, thanks a lot, I do have a tree on github
Hi Javier,
On 10/07/2015 07:25 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/07/2015 01:05 PM, Yakir Yang wrote:
Hi Javier,
On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/07/2015 11:02 AM, Yakir Yang wrote:
Hi Javier,
On 10/07/2015 04:46 PM, Javier
Hi Javier,
On 10/20/2015 05:48 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/20/2015 04:10 AM, Yakir Yang wrote:
Hi Javier,
On 10/19/2015 06:40 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/10/2015 05:35 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP
Hi Javier,
On 10/19/2015 06:40 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/10/2015 05:35 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Remove the empty line at the end of do
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6: None
Changes in v5:
clock-names = "24m";
#phy-cells = <0>;
};
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4:
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Cha
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6:
- Fix Peach Pit hpd property name error:
- hpd-
From: Mark Yao <y...@rock-chips.com>
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao <y...@rock-chips.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
C
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6:
- Fix the wron
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr va
Hi Javier,
On 10/08/2015 08:40 AM, Yakir Yang wrote:
On 10/07/2015 07:25 PM, Javier Martinez Canillas wrote:
On 10/07/2015 01:05 PM, Yakir Yang wrote:
On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
On 10/07/2015 11:02 AM, Yakir Yang wrote:
On 10/07/2015 04:46 PM, Javier Martinez
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP h
-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
to get the backword timing values. Krzysztof suggest me that driver could use
the "of_property_read_bool
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes
, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
Changes in v3:
- The link_rate and lane_count shouldn't config to the DT property
Hi Krzysztof,
On 10/10/2015 11:46 PM, Yakir Yang wrote:
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.
But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup
On 10/12/2015 08:49 AM, Krzysztof Kozlowski wrote:
On 12.10.2015 09:37, Yakir Yang wrote:
Hi Krzysztof,
On 10/10/2015 11:46 PM, Yakir Yang wrote:
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video
On 10/12/2015 02:54 PM, Krzysztof Kozlowski wrote:
On 12.10.2015 13:29, Yakir Yang wrote:
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.
But presumably Exynos still relies on the DT
-by: Yakir Yang <y...@rock-chips.com>
---
*just add a note that this is v7 of only fifth patch.*
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
to avoid -
On 10/12/2015 11:51 AM, Krzysztof Kozlowski wrote:
On 12.10.2015 11:43, Yakir Yang wrote:
On 10/12/2015 08:49 AM, Krzysztof Kozlowski wrote:
On 12.10.2015 09:37, Yakir Yang wrote:
Hi Krzysztof,
On 10/10/2015 11:46 PM, Yakir Yang wrote:
Both hsync/vsync polarity and interlace mode can
Hi Kishon
On 10/12/2015 11:02 PM, Kishon Vijay Abraham I wrote:
Hi,
On Saturday 10 October 2015 09:25 PM, Yakir Yang wrote:
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly
Hi Kishon,
On 10/13/2015 06:28 AM, Kishon Vijay Abraham I wrote:
Hi,
On Saturday 10 October 2015 09:28 PM, Yakir Yang wrote:
This phy driver is binded with the Rockchip DisplayPort
driver, here are the brief properties:
edp_phy: edp-phy@ff770274 {
compatible
/next/linux-next.git when I'm preparing v4 series.
Thanks,
- Yakir
Regards,
Romain
2015-08-21 15:16 GMT+02:00 Thierry Reding tred...@nvidia.com:
On Fri, Aug 21, 2015 at 08:24:16PM +0900, Jingoo Han wrote:
On 2015. 8. 21., at PM 7:01, Yakir Yang y...@rock-chips.com wrote:
Hi Jingoo,
在 2015/8/21
, Yakir Yang y...@rock-chips.com wrote:
+ -analogix,color-depth:
+ number of bits per colour component.
+ COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
This seems pretty generic. Just use 6, 8, 10, or 12 for values. And
drop the vendor prefix
Hi Thierry,
在 2015/8/25 17:15, Thierry Reding 写道:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring wrote:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang y...@rock-chips.com wrote:
[...]
+ -analogix,link-rate:
+ max link rate supported by the eDP controller
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v4:
- Take Romain s
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v4:
- Take Thierry suggest, seprate the link-rate and lane-count limit
out with the device_typ
, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v4:
- Take Jingoo Han suggest, update commit message more readable.
- Adjust the order from 05 to 04
Changes in v3:
- Take Thierry Reding suggest, link_rate and lane_count shouldn't config to
the DT property
provide the backward compatibility, so there are no
bisectability break that make this change in a separate patch.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v4:
- Take Krzysztof suggest, separate all DTS changes to a separate patch.
Changes in v3: None
Changes in v2: None
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v4:
- Remove some deprecated DT properties in rockchip dp document.
C
() in to achieve the compatibility hacks.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v4:
- Take Krzysztof suggest, provide backword compatibility with samsung.
- Take Thierry suggest, add "color-depth" and "color-space" dynamic parsed.
Changes in
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v4:
From: Mark Yao <y...@rock-chips.com>
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao <y...@rock-chips.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
C
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Cha
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
drivers/gpu/drm/
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v4:
- Call drm_panel_prepare() in .get
After run "checkpatch.pl -f --subjective" command, I see there
are lots of alignment problem in exynos_dp driver, so let just
fix them.
- Take Romain suggest, rebase on linux-next branch
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v4: None
Changes in v3: No
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Add GNU license v2 declared and samsung copyright
drivers/gpu/drm/exynos/exynos_dp.c | 1 +
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 1 +
include/drm/
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v4:
- Take Jingoo suggest, add commit messages.
Changes i
Hi Heiko,
在 09/02/2015 12:51 AM, Heiko Stuebner 写道:
Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip
Heiko,
在 09/02/2015 04:46 AM, Heiko Stuebner 写道:
Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
Split the dp core driver from exynos directory to bridge
directory, and rename the core driver to analogix_dp_*,
leave the platform code to analogix_dp-exynos.
Signed-off-by: Yakir
Hi Heiko,
在 09/02/2015 04:58 AM, Heiko Stuebner 写道:
Hi Yakir,
small nit more below
Am Dienstag, 1. September 2015, 18:51:16 schrieb Heiko Stuebner:
Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
+- clocks: from common clock binding: handle to dp clock.
+ of memory mapped
Hi Heiko,
在 09/02/2015 05:00 AM, Heiko Stuebner 写道:
Hi Yakir,
Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
From: Mark Yao <y...@rock-chips.com>
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to conf
Hi Heiko,
在 09/02/2015 05:00 AM, Heiko Stuebner 写道:
Hi Yakir,
Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off
Hi Heiko,
在 09/02/2015 05:47 AM, Heiko Stuebner 写道:
Hi Yakir,
Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge
Hi Krzysztof,
在 09/07/2015 08:22 AM, Krzysztof Kozlowski 写道:
On 06.09.2015 16:49, Yakir Yang wrote:
Hi Krzysztof,
在 09/04/2015 08:41 AM, Krzysztof Kozlowski 写道:
On 03.09.2015 14:30, Yakir Yang wrote:
Hi Krzysztof,
在 09/03/2015 08:58 AM, Krzysztof Kozlowski 写道:
On 01.09.2015 14:49, Yakir
Hi Krzysztof,
在 09/07/2015 07:55 AM, Krzysztof Kozlowski 写道:
On 06.09.2015 13:07, Yakir Yang wrote:
Hi Krzysztof,
在 09/04/2015 08:36 AM, Krzysztof Kozlowski 写道:
On 01.09.2015 15:07, Yakir Yang wrote:
Empty commit message. Please explain here why you want to add platform
device type support
Hi Thierry,
在 09/03/2015 04:38 PM, Thierry Reding 写道:
On Wed, Sep 02, 2015 at 06:02:25PM +0800, Yakir Yang wrote:
在 2015/9/2 16:34, Thierry Reding 写道:
[...]
At the very least your code must compile when applied against a recent
upstream tree. I would also expect you to make sure the code
Hi Krzysztof,
在 09/03/2015 04:04 PM, Krzysztof Kozlowski 写道:
On 01.09.2015 14:55, Yakir Yang wrote:
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code, same to color space and color depth can
Hi Krzysztof,
在 09/04/2015 08:36 AM, Krzysztof Kozlowski 写道:
On 01.09.2015 15:07, Yakir Yang wrote:
Empty commit message. Please explain here why you want to add platform
device type support.
Actually the title is confusing. You are not adding support for platform
device types but rather
Hi Joe,
在 09/03/2015 01:57 PM, Joe Perches 写道:
On Thu, 2015-09-03 at 13:33 +0800, Yakir Yang wrote:
[]
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
[]
@@ -155,24 +156,22 @@ static int exynos_dp_read_edid(struct
exynos_dp_device *dp
Hi Heiko,
在 09/03/2015 09:52 PM, Heiko Stuebner 写道:
Am Donnerstag, 3. September 2015, 11:25:00 schrieb Yakir Yang:
在 09/02/2015 09:27 PM, Rob Herring 写道:
On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang <y...@rock-chips.com> wrote:
+- clocks: from common clock binding: handle to dp
Hi Emil,
在 09/02/2015 10:50 PM, Emil Velikov 写道:
[Dropping the CC list]
Hmm...Don't understand what this means. If you can explain, that
would be better, so I would not miss your suggest. :-)
Hi Yakir Yang,
On 1 September 2015 at 06:49, Yakir Yang <y...@rock-chips.com> wrote:
Hi Rob,
在 09/02/2015 09:27 PM, Rob Herring 写道:
On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang <y...@rock-chips.com> wrote:
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on ro
Hi Rob,
在 09/03/2015 04:17 AM, Rob Herring 写道:
On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <y...@rock-chips.com> wrote:
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is a property of the panel (or connector perhap
Hi Krzysztof,
在 09/03/2015 08:58 AM, Krzysztof Kozlowski 写道:
On 01.09.2015 14:49, Yakir Yang wrote:
Split the dp core driver from exynos directory to bridge
directory, and rename the core driver to analogix_dp_*,
leave the platform code to analogix_dp-exynos.
Signed-off-by: Yakir Yang &l
Hi Krzysztof,
在 09/03/2015 08:21 AM, Krzysztof Kozlowski 写道:
On 01.09.2015 14:46, Yakir Yang wrote:
After run "checkpatch.pl -f --subjective" command, I see there
are lots of alignment problem in exynos_dp driver, so let just
fix them.
Hi,
Warnings from checkpatch are no
Hi Krzysztof,
在 09/03/2015 01:08 PM, Krzysztof Kozlowski 写道:
On 03.09.2015 14:04, Yakir Yang wrote:
Hi Krzysztof,
在 09/03/2015 08:21 AM, Krzysztof Kozlowski 写道:
On 01.09.2015 14:46, Yakir Yang wrote:
After run "checkpatch.pl -f --subjective" command, I see there
are lots of
Thierry,
在 2015/9/2 16:34, Thierry Reding 写道:
On Wed, Sep 02, 2015 at 10:06:36AM +0800, Yakir Yang wrote:
在 09/02/2015 05:00 AM, Heiko Stuebner 写道:
Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
[...]
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
b/drivers/gpu/drm
Hi Heiko,
在 2015/9/1 22:24, Heiko Stuebner 写道:
Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang &l
Hi Krzysztof,
在 09/04/2015 08:41 AM, Krzysztof Kozlowski 写道:
On 03.09.2015 14:30, Yakir Yang wrote:
Hi Krzysztof,
在 09/03/2015 08:58 AM, Krzysztof Kozlowski 写道:
On 01.09.2015 14:49, Yakir Yang wrote:
Split the dp core driver from exynos directory to bridge
directory, and rename the core
Hi Rob,
在 09/05/2015 05:46 AM, Rob Herring 写道:
On Wed, Sep 2, 2015 at 11:27 PM, Yakir Yang <y...@rock-chips.com> wrote:
Hi Rob,
在 09/03/2015 04:17 AM, Rob Herring 写道:
On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <y...@rock-chips.com> wrote:
Some edp screen do not have hpd signal,
Hi Krzysztof,
On 09/30/2015 01:17 PM, Krzysztof Kozlowski wrote:
On 22.09.2015 16:29, Yakir Yang wrote:
Split the dp core driver from exynos directory to bridge directory,
and rename the core driver to analogix_dp_*, rename the platform
code to exynos_dp.
Beside the new analogix_dp driver
Hi Krzysztof,
On 09/30/2015 01:22 PM, Krzysztof Kozlowski wrote:
On 22.09.2015 16:34, Yakir Yang wrote:
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
C
Hi Krzysztof,
On 09/30/2015 01:39 PM, Krzysztof Kozlowski wrote:
On 22.09.2015 16:43, Yakir Yang wrote:
After exynos_dp have been split the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some Samsung platform properties which
could be dynamically parsed from
Hi Krzysztof,
On 09/30/2015 04:26 PM, Krzysztof Kozlowski wrote:
On 30.09.2015 17:20, Yakir Yang wrote:
Hi Krzysztof,
On 09/30/2015 03:34 PM, Krzysztof Kozlowski wrote:
On 30.09.2015 16:19, Yakir Yang wrote:
Hi Krzysztof,
On 09/30/2015 01:32 PM, Krzysztof Kozlowski wrote:
On 22.09.2015 16
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Cha
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v5: None
Changes in v4:
- Seprate the link-rate and lane-count limit out with the device_type
or name list no changed (Jingoo)
- Remove new copyright (Jingoo)
- Fix compiled failed due to analogix_dp_device misspell
- Improved commit message more readable, and avoid using some
uncommon style like bellow: (Joe Preches)
- retval = exynos_dp_read_bytes_from_i2c(...
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell
clock-names = "24m";
#phy-cells = <0>;
};
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock required
elemets in
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v5: None
Changes in v4:
- Call drm_panel_p
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v5:
- Correct the misspell in commit message. (Krzysztof)
Changes in v4:
- Separate all DTS changes to a separate
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v5:
- Remove the empty line at the end of document, and correct the en
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v5: None
Changes in v4:
- Take Jingoo suggest, add com
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v5:
- Resequence this patch after analogix_dp driver have been split
from exynos_dp code, and re
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property.
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes
, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
Changes in v3:
- The link_rate and lane_count shouldn't config to the DT property value
directly, but
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v5: None
Changes
Hi Thierry,
Thanks for your suggest :)
On 09/21/2015 05:15 PM, Thierry Reding wrote:
On Mon, Sep 21, 2015 at 04:45:44PM +0800, Yakir Yang wrote:
Hi Heiko,
On 09/02/2015 10:15 AM, Yakir Yang wrote:
Hi Heiko,
在 09/02/2015 05:47 AM, Heiko Stuebner 写道:
Hi Yakir,
Am Dienstag, 1. September
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
---
Changes in v1
-by: Yakir Yang <y...@rock-chips.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7:
- Back to use the of_property_read_bool() interfacs t
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v10: None
Changes in v9:
- Document
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes
From: Mark Yao <y...@rock-chips.com>
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao <y...@rock-chips.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v10:
- Fix the wrong
led.
- move dp hpd detect to connector detect function.
- Add edid modes parse support
Changes in v2:
- Remove new copyright (Jingoo)
- Fix compiled failed due to analogix_dp_device misspell
- Improved commit message more readable, and avoid using some
uncommon style like bellow: (Joe Preches)
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
Tested-by: Javier Martinez Canillas <jav...@
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
---
Ch
, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit
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