On 09/12/2017 11:20 AM, Eugeniy Paltsev wrote:
DW sdio controller has external ciu clock divider controlled
via register in SDIO IP. It divides sdio_ref_clk
(which comes from CGU) by 16 for default. So default mmcclk
clock (which comes to sdk_in) is 2500 Hz.
So fix wrong current value
DW sdio controller has external ciu clock divider controlled
via register in SDIO IP. It divides sdio_ref_clk
(which comes from CGU) by 16 for default. So default mmcclk
clock (which comes to sdk_in) is 2500 Hz.
So fix wrong current value (5000 Hz) to actual 2500 Hz.
Signed-off-by:
