Re: [PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency

On Tue, 2017-09-12 at 11:38 -0700, Vineet Gupta wrote: > On 09/12/2017 11:20 AM, Eugeniy Paltsev wrote: > > DW sdio controller has external ciu clock divider controlled > > via register in SDIO IP. It divides sdio_ref_clk > > (which comes from CGU) by 16 for default. So default mmcclk > > clock

[PATCH] ARC: Memory barriers for everyone!

By default __iormb() and __iowmb() translate into a do { } while(0) for AXS10x platform. As ARC700 supports the sync op we can use the standard memory barriers that are supplied by asm-generic headers. Signed-off-by: Jose Abreu Cc: Vineet Gupta Cc: