Re: [RFC 0/6] glibc port to ARC architecture

On Mon, 27 Nov 2017, Vineet Gupta wrote: > > Any new port should have support added to build-many-glibcs.py for all > > ABIs supported by the port (e.g. both endiannesses, if you support both BE > > and LE, and any other ABI variants). > > build-many-glibcs.py works for ARC now - after the 2

Re: [RFC 0/6] glibc port to ARC architecture

On 06/27/2017 05:00 AM, Joseph Myers wrote: On Tue, 27 Jun 2017, Florian Weimer wrote: On 06/27/2017 10:00 AM, Vineet Gupta wrote: This is a Request for comments for glibc port to ARC architecture. http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx The Linux kernel,

[PATCH 2/4] ARC: [plat-hsdk]: Get rid of core pll frequency set in platform code

Get rid of core pll frequency set in platform code as we set it via device tree using 'assigned-clock-rates' property. Signed-off-by: Eugeniy Paltsev --- arch/arc/plat-hsdk/platform.c | 42 -- 1 file changed, 42 deletions(-)

[PATCH 3/4] ARC: [plat-axs103]: Set initial core pll output frequency

Set initial core pll output frequency specified in device tree to 100MHz for SMP configuration and 90MHz for UP configuration. It will be applied at the core pll driver probing. Update platform quirk for decreasing core frequency for quad core configuration. Signed-off-by: Eugeniy Paltsev

[PATCH 4/4] ARC: [plat-axs103] refactor the quad core DT quirk code

Refactor the quad core DT quirk code: get rid of waste division and multiplication by 100 constant. Signed-off-by: Eugeniy Paltsev --- arch/arc/plat-axs10x/axs10x.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git

[PATCH 0/4] ARC: Set initial core pll output frequency via DTS

Set initial core pll output frequency on HSDK and AXS103 via "assigned-clock-rates" property in device tree. It will be applied at the core pll driver probing. Eugeniy Paltsev (4): ARC: [plat-hsdk]: Set initial core pll output frequency ARC: [plat-hsdk]: Get rid of core pll frequency set in

[PATCH 1/4] ARC: [plat-hsdk]: Set initial core pll output frequency

Set initial core pll output frequency specified in device tree to 1GHz. It will be applied at the core pll driver probing. Signed-off-by: Eugeniy Paltsev --- arch/arc/boot/dts/hsdk.dts | 8 1 file changed, 8 insertions(+) diff --git

Re: [PATCH] frv: fix build failure

+CC linux-arch, Arnd On 11/23/2017 09:17 AM, Alexey Brodkin wrote: Hi Sudip, On Tue, 2017-11-21 at 22:10 +, Sudip Mukherjee wrote: The frv defconfig build is failing with the error: lib/mpi/mpih-div.o: In function `mpihelp_divrem': mpih-div.c:(.text+0x30c): undefined reference to `abort'