On Tue, 2017-11-14 at 15:46 -0800, sb...@codeaurora.org wrote:
> On 11/14, Alexey Brodkin wrote:
> > Hi Vladimir,
> >
> > On Tue, 2017-11-14 at 19:01 +0200, Vladimir Zapolskiy wrote:
> > > On 11/14/2017 02:20 PM, Eugeniy Paltsev wrote:
> > > >
> > > > Add option to set initial output frequency of
Set initial core pll output frequency specified in device tree to
100MHz for SMP configuration and 90MHz for UP configuration.
It will be applied at the core pll driver probing.
Update platform quirk for decreasing core frequency for quad core
configuration.
Signed-off-by: Eugeniy Paltsev
---
a
Get rid of core pll frequency set in platform code as we set it via
device tree using 'assigned-clock-rates' property.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/plat-hsdk/platform.c | 42 --
1 file changed, 42 deletions(-)
diff --git a/arch/arc/plat-hsd
Set initial core pll output frequency on HSDK and AXS103 via
"assigned-clock-rates" property in device tree.
It will be applied at the core pll driver probing.
Eugeniy Paltsev (4):
ARC: [plat-hsdk]: Set initial core pll output frequency
ARC: [plat-hsdk]: Get rid of core pll frequency set in
Set initial core pll output frequency specified in device tree to
1GHz. It will be applied at the core pll driver probing.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/boot/dts/hsdk.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts/hsdk
Refactor the quad core DT quirk code:
get rid of waste division and multiplication by 100 constant.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/plat-axs10x/axs10x.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-ax
On Mon 2017-12-04 11:50:40, Jose Abreu wrote:
> Hi Alexey,
>
> On 04-12-2017 11:32, Alexey Brodkin wrote:
> > My first [probably incorrect] assumption is Xserver requires fbdev
> > (/dev/fbX)
> > and it cannot use DRI video card natively. Is that correct?
> >
> >
>
> Xserver can use DRI directly
