On Wednesday, March 12, 2014 7:31:26 PM UTC-5, Julian Calaby wrote:
> Should this have PC20 twice?
>
Prepare for v2 of patches. This time, I hope I'll get the CC's right.
Alex
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Hi Dennis,
On 03/14/2014 09:17 PM, Dennis Gilmore wrote:
> On Fri, 14 Mar 2014 10:16:42 -0400
> Tom Rini wrote:
>
>> On Fri, Mar 14, 2014 at 10:33:32AM +, Ian Campbell wrote:
>>
>>> Hi,
>>>
>>> This is my first cut at an upstreamable series based upon the
>>> https://github.com/linux-sunxi/u
Hi,
On 03/07/2014 03:58 AM, Ian Campbell wrote:
> Following eca3aeb352c9 "Licenses: introduce SPDX Unique Lincense Identifiers"
> switch sunxi files to use SPDX license identifiers. As with that changeset,
> this patch is supposed to be only a change to the textual representation of
> the
> licen
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 03/14/2014 09:17 AM, Tom Rini wrote:
> On Fri, Mar 14, 2014 at 10:33:46AM +, Ian Campbell wrote:
>> +#ifdef CONFIG_SPL_BUILD +void sunxi_board_init(void) +{ + int
>> power_failed = 0; + unsigned long ramsize; + + printf("DRAM:"); +
>> ra
On Sat, Mar 15, 2014 at 04:45:08PM +0100, Hans de Goede wrote:
> Hi,
>
> Thanks for your continued work on this.
>
> On 03/15/2014 04:43 PM, Carlo Caione wrote:
> > Signed-off-by: Hans de Goede
> > Signed-off-by: Carlo Caione
> > ---
> > arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 12 +++
Hi,
Thanks for your continued work on this.
On 03/15/2014 04:43 PM, Carlo Caione wrote:
> Signed-off-by: Hans de Goede
> Signed-off-by: Carlo Caione
> ---
> arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 12
> arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 13 +
>
AXP209 and AXP202 are the PMUs (Power Management Unit) used by A10, A13
and A20 SoCs and developed by X-Powers, a sister company of Allwinner.
AXP20x comprises an adaptive USB-Compatible PWM charger, 2 BUCK DC-DC
converters, 5 LDOs, multiple 12-bit ADCs of voltage, current and temperature
as well a
AXP202 and AXP209 come with two synchronous step-down DC-DCs and five
LDOs. This patch introduces basic support for those regulators.
Signed-off-by: Carlo Caione
---
drivers/regulator/Kconfig| 7 +
drivers/regulator/Makefile | 1 +
drivers/regulator/axp20x-regulator.c |
Add ABI entries for the PEK found on PMU X-Powers AXP202 and AXP209.
Signed-off-by: Carlo Caione
---
Documentation/ABI/testing/sysfs-driver-input-axp-pek | 11 +++
1 file changed, 11 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-driver-input-axp-pek
diff --git a/Docu
This patch introduces the preliminary support for PMICs X-Powers AXP202
and AXP209. The AXP209 and AXP202 are the PMUs (Power Management Unit)
used by A10, A13 and A20 SoCs and developed by X-Powers, a sister company
of Allwinner.
The core enables support for two subsystems:
- PEK (Power Enable Ke
Signed-off-by: Hans de Goede
Signed-off-by: Carlo Caione
---
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 12
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 13 +
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 12
3 files changed, 37 insertions(+)
Signed-off-by: Carlo Caione
---
arch/arm/configs/sunxi_defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 3e2259b..0cef101 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
This dtsi describes the axp209 PMIC, and is to be included from inside
the i2c controller node to which the axp209 is connected.
Signed-off-by: Hans de Goede
Signed-off-by: Carlo Caione
---
arch/arm/boot/dts/x-powers-axp209.dtsi | 60 ++
1 file changed, 60 insert
Bindings documentation for the AXP20x driver. In this file also two
sub-nodes (PEK and regulators) are documented.
Signed-off-by: Carlo Caione
---
Documentation/devicetree/bindings/mfd/axp20x.txt | 83 ++
.../devicetree/bindings/vendor-prefixes.txt| 1 +
2 files ch
This patch add support for the Power Enable Key found on MFD AXP202 and
AXP209. Besides the basic support for the button, the driver adds two
entries in sysfs to configure the time delay for power on/off.
Signed-off-by: Carlo Caione
---
drivers/input/misc/Kconfig | 11 ++
drivers/input/mis
Hi All,
I've just updated:
https://github.com/linux-sunxi/linux-sunxi/commits/sunxi-devel
to 3.14-rc6
Besides rebasing to 3.14-rc6, this contains the following over the previous
sunxi-devel branch update:
-core irq change to allow eoi after threaded interrupt handler completion
-sun7i nmi irq co
On Sat, Mar 15, 2014 at 11:29 AM, Ivan Kozic wrote:
> Hi John,
>
> Wow thanks - this looks quite cool - it seems that they've started working
> on YUV422 16bit and CCIR656 as well. May I ask where did you find the
> driver?
It is from the current Allwinner Android tree. The CSI driver in sunxi
is
Hi John,
Wow thanks - this looks quite cool - it seems that they've started working
on YUV422 16bit and CCIR656 as well. May I ask where did you find the
driver?
One crucial file is missing - sun4i_csi_core.h or sunxi_csi_core.h I guess,
as it's not for A10 anymore.
On Saturday, March 15, 2014
Now that we only ack irq 0 the code can be simplified a lot.
Also switch from read / modify / write to a simple write clear:
1) This is what the android code does (it has a hack for acking irq 0
in its unmask code doing this)
2) read / modify / write simply does not make sense for an irq status
Since the sun4i irq chip does not require any action and clears the interrupt
when the level goes back to inactive, we don't need to mask / unmask for
non oneshot IRQs, to achieve this we make sun4i_irq_ack a nop for all irqs
except irq 0 and use handle_fasteoi_irq for all interrupts.
Now there mi
Hi All,
Here is v2 of my patchset for sun4i-irq.c to use handle_fasteoi_irq for all
irqs + follow up clean-up patch.
Changes since v2:
-adjust commit msg based on Thomas' comments, and merge patch 1 and 2 as
they make more sense as 1 patch
Regards,
Hans
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Allwinner A20/A31 SoCs have special registers to control / (un)mask /
acknowledge NMI. This NMI controller is separated and independent from GIC.
This patch adds a new irqchip to manage NMI.
Signed-off-by: Carlo Caione
Acked-by: Maxime Ripard
---
drivers/irqchip/Makefile| 1 +
drivers
This patch adds DTS entries for NMI controller as child of GIC.
Signed-off-by: Carlo Caione
---
arch/arm/boot/dts/sun6i-a31.dtsi | 9 +
arch/arm/boot/dts/sun7i-a20.dtsi | 9 +
2 files changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun
Added documentation for NMI irqchip.
Signed-off-by: Carlo Caione
---
.../allwinner,sun67i-sc-nmi.txt| 27 ++
1 file changed, 27 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt
diff --gi
Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI.
Three register are present to (un)mask, control and acknowledge NMI.
These two patches add a new irqchip driver in cascade with GIC.
Changes since v1:
- added binding document
Changes since v2:
- fixed tr
Hi Nuke.
>>Now take the resulting 'u-boot' file, and use it as the coreboot payload.
Install as usual and monitor the serial console
How to install u-boot to sdcard?.
Regards
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