On Fri, Oct 31, 2014 at 06:05:22PM +0800, Herbert Xu wrote:
> On Fri, Oct 31, 2014 at 10:57:06AM +0100, Maxime Ripard wrote:
> >
> > On a 3.18-rc2 kernel:
> >
> > $ git grep kmap -- crypto/
> > crypto/ahash.c: walk->data = kmap(walk->pg);
> > crypto/ahash.c:
Hi
I am trying to bring up HDMI support for banana PI on kernel 3.14.6 and i
could not find the HDMI driver.
I find that the drivers are there at:
https://github.com/linux-sunxi/linux-sunxi/blob/lichee-3.0.8-sun4i/drivers/video/sun4i/hdmi/aw/hdmi_core.c
https://github.com/amery/linux-sunxi/tr
Good Morning!
I use the following repository
git clone https://github.com/jwrdegoede/u-boot-sunxi.git -b sunxi-wip
u-boot-sunxi-wip
make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- Cubieboard2_config
make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
And for the record SD
dd if=u-boot-sunx
Good Morning!
To drive the HDMI function depends on various factors
you can take a look
here http://linux-sunxi.org/Linux_mainlining_effort#Core_Stuff
Att:
Ezaul Zillmer
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On Mon, Nov 03, 2014 at 10:34:46AM +0100, Maxime Ripard wrote:
> What I mean is that since you are saying that drivers should do the
> kmap themselves, then *all* of the drivers are broken if they are not
> using it. And all of them are missing this kmap.
kmap is used by the software implementatio
Hi,
there is no display support in mainline kernel.
The latest kernel, that supports display is the sunxi-3.4 kernel of the
linux-sunxi community.
Regards
Am 03.11.2014 10:55, schrieb Prajosh Premdas:
Hi
I am trying to bring up HDMI support for banana PI on kernel 3.14.6
and i could not find
How do I reduce the clock frequency for testing?
Dennis
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For more optio
In preparation for adding sun6i dram support.
Signed-off-by: Hans de Goede
---
arch/arm/cpu/armv7/sunxi/Makefile| 6 +-
arch/arm/cpu/armv7/sunxi/dram.c | 750 ---
arch/arm/cpu/armv7/sunxi/dram_sun4i.c| 750 +++
ar
Add full support for dram initialization, using a fixed clock and autodetection
of the memory organization (numbers of channels, bus-width, etc.).
This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK,
extended with extra initialization sequences and the autodetect algorith
From: Oliver Schinagl
The A31 uses a new push-pull two wire interface, which features higher
transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8
bytes each time, this driver will only see very little use and thus is
limited to single byte transmission only.
Signed-off-by: Oliv
Hi All,
After spending a lot of time on this, I'm happy to present this patch series
adding A31 dram init and SPL support, allowing one to boot Allwinner A31
boards using just u-boot for all stages of the boot :)
Please review, I will add these to u-boot-sunxi/next and send a pull-req
as soon as
Add clock_init_safe and clockset_pll5 functions, as these are needed for
SPL support resp. DRAM init (which is needed for SPL too).
Also add some extra clock register constant defines.
Signed-off-by: Hans de Goede
---
arch/arm/cpu/armv7/sunxi/clock_sun6i.c| 77 ++
From: Oliver Schinagl
The A31 uses the AXP221 pmic for various voltages.
Signed-off-by: Oliver Schinagl
Signed-off-by: Hans de Goede
---
board/sunxi/board.c| 14 ++
configs/Colombus_defconfig | 1 +
drivers/power/Makefile | 1 +
drivers/power/axp221.c | 103 ++
Without this the cache will only work in write-through mode, and as soon as
it is put in write-back mode things break.
Signed-off-by: Hans de Goede
---
arch/arm/cpu/armv7/sunxi/board.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/
Not used atm, for future use (e.g. PSCI).
Signed-off-by: Hans de Goede
---
arch/arm/include/asm/arch-sunxi/cpu.h| 5 +++
arch/arm/include/asm/arch-sunxi/cpucfg.h | 67
2 files changed, 72 insertions(+)
create mode 100644 arch/arm/include/asm/arch-sunxi/cpuc
Signed-off-by: Hans de Goede
---
board/sunxi/Kconfig | 4
board/sunxi/MAINTAINERS | 1 +
configs/Mele_M9_defconfig | 9 +
3 files changed, 14 insertions(+)
create mode 100644 configs/Mele_M9_defconfig
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index df47863..f60
Enable the SPL now that we've all the necessary bits in place.
Signed-off-by: Hans de Goede
---
board/sunxi/Kconfig| 1 +
configs/Colombus_defconfig | 9 +
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 905e62d..df47
El 2014-10-31 16:47, Siarhei Siamashka escribió:
On Fri, 31 Oct 2014 13:59:19 +0100
Oscar wrote:
Hi,
Did anyone use u-boot 2014.10 from mainline on a A20 board
(cubieboard2)?
Yes, it works. Though some things are a bit different if compared
with https://github.com/linux-sunxi/u-boot-sunxi
Hi,
On Mon, Nov 3, 2014 at 11:34 PM, Hans de Goede wrote:
> From: Oliver Schinagl
>
> The A31 uses a new push-pull two wire interface, which features higher
> transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8
> bytes each time, this driver will only see very little use and t
On Mon, Nov 3, 2014 at 11:34 PM, Hans de Goede wrote:
> In preparation for adding sun6i dram support.
>
> Signed-off-by: Hans de Goede
> ---
> arch/arm/cpu/armv7/sunxi/Makefile| 6 +-
> arch/arm/cpu/armv7/sunxi/dram.c | 750
> ---
> arch/arm/cp
Hi,
On Mon, Nov 3, 2014 at 11:34 PM, Hans de Goede wrote:
> Not used atm, for future use (e.g. PSCI).
>
> Signed-off-by: Hans de Goede
> ---
> arch/arm/include/asm/arch-sunxi/cpu.h| 5 +++
> arch/arm/include/asm/arch-sunxi/cpucfg.h | 67
>
> 2 files change
Slowing the clock Frequency down to 900Mhz seems to have fixed the problem.
I will continue testing
Dennis
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Unlike previous Allwinner SoCs, there is no central PHY control block
on the A80. Also, OTG support is completely split off into a different
controller.
This adds a new driver to support the regular USB PHYs.
Signed-off-by: Chen-Yu Tsai
---
.../devicetree/bindings/phy/sun9i-usb-phy.txt |
Signed-off-by: Chen-Yu Tsai
---
This patch does not use sunxi-common-regulators.dtsi, but adds the
regulators directly. To use the common regulators file, we would
need to use phandles and switch to preprocessor includes to support
that.
---
arch/arm/boot/dts/sun9i-a80-optimus.dts | 72 +
The USB controller/phy clocks and reset controls are in a separate
address block, unlike previous SoCs where they were in the clock
controller.
This patch copies the original gates clk functions used for usb
clocks into a separate file, and renames them to *_usb_*. Also
add a per-gate parent index
The USB controller and phy clocks and resets have a separate address
block and driver. Add the nodes to represent them.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/
The A80 has 3 EHCI/OHCI USB controllers.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 70
1 file changed, 70 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 1a80e09..b6f344f 10064
On sun9i, there are 3 independent usb phys. Add device nodes for them.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 37 +
1 file changed, 37 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
i
Hi everyone,
This series adds USB host controller (EHCI/OHCI) support for the Allwinner
A80 SoC. The A80 has 3 pairs of host controllers and USB PHYs. The PHYs,
unlike in previous SoCs, do not have low level control registers anymore.
As such, this series forgoes the original phy-sun4i-usb driver
Hi Hans,
On Tue, Nov 4, 2014 at 2:34 AM, Hans de Goede wrote:
> In preparation for adding sun6i dram support.
>
> Signed-off-by: Hans de Goede
> ---
> arch/arm/cpu/armv7/sunxi/Makefile| 6 +-
> arch/arm/cpu/armv7/sunxi/dram.c | 750
> ---
> ar
Hy Wens,
This is some really old work, and I'm assuming hans picked it up, as I
never tested the code (didn't have hardware at the time)
I'll comment as I remember it and hope that helps.
On a side note, do we know what p2wi stands for? I'm guessing 2wi is
allwinners try at combining the nam
On Tue, 2014-11-04 at 12:07 +0800, Chen-Yu Tsai wrote:
> Unlike previous Allwinner SoCs, there is no central PHY control block
> on the A80. Also, OTG support is completely split off into a
> different
> controller.
>
> This adds a new driver to support the regular USB PHYs.
>
> Signed-off-by:
Hi,
On Tue, Nov 4, 2014 at 2:10 PM, Olliver Schinagl wrote:
> Hy Wens,
>
> This is some really old work, and I'm assuming hans picked it up, as I never
> tested the code (didn't have hardware at the time)
I believe Hans did pick it up for u-boot-sunxi, and now we're just mainlining
it.
> I'll c
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