Hi,
On Sun, Feb 1, 2015 at 3:17 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Wed, Jan 28, 2015 at 03:54:11AM +0800, Chen-Yu Tsai wrote:
The A80 has 3 EHCI/OHCI USB controllers.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun9i-a80.dtsi | 70
On Tue, Jan 27, 2015 at 11:31:26AM -0800, Dmitry Torokhov wrote:
Ah right, looking at the code again I see we use
devm_input_allocate_device()
is there no devm_create_file for creating sysfs entries ?
Greg was pushing the viewpoint that no drivers should create device attributes
On Wed, Jan 28, 2015 at 03:54:06AM +0800, Chen-Yu Tsai wrote:
The USB clocks originally shared code with the gates clocks, but had
additional reset controllers. Move these to a separate file. This will
allow us to add new support for slightly different USB clocks, such as
on the A80, without
On Wed, Jan 28, 2015 at 03:54:12AM +0800, Chen-Yu Tsai wrote:
Some SoCs have a total of 4 possible USB controllers. One such example
is the A80, which has one USB3 dual role device and 3 EHCI/OHCI pairs.
Add a common VBUS regulator for the last host controller.
Signed-off-by: Chen-Yu Tsai
On Wed, Jan 28, 2015 at 03:54:10AM +0800, Chen-Yu Tsai wrote:
On sun9i, there are 3 independent usb phys for EHCI/OHCI.
Add device nodes for them.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android
On Wed, Jan 28, 2015 at 03:54:09AM +0800, Chen-Yu Tsai wrote:
Unlike previous Allwinner SoCs, there is no central PHY control block
on the A80. Also, OTG support is completely split off into a different
controller.
This adds a new driver to support the regular USB PHYs.
Signed-off-by:
On Wed, Jan 28, 2015 at 03:54:07AM +0800, Chen-Yu Tsai wrote:
The USB controller/phy clocks and reset controls are in a separate
address block, unlike previous SoCs where they were in the clock
controller. Also, access to the address block is controlled by a
clock gate to AHB.
Add support
On Wed, Jan 28, 2015 at 03:54:11AM +0800, Chen-Yu Tsai wrote:
The A80 has 3 EHCI/OHCI USB controllers.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun9i-a80.dtsi | 70
1 file changed, 70 insertions(+)
diff --git
On Wed, Jan 28, 2015 at 03:54:08AM +0800, Chen-Yu Tsai wrote:
The USB controller and phy clocks and resets have a separate address
block and driver. Add the nodes to represent them.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded
I don't see thousands of A31 boards users eagerly waiting for
mainline.
I don't see thousands of A10s boards users eagerly waiting for
mainline either. I don't even see the point you're trying to make
actually.
I can't speak for him, but of all the boards available, the most
attractive to
This is a low-cost Allwinner A20 board with Arduino-style GPIO headers;
it features 1G RAM, 4G NAND flash, 1 micro-SD, 2 USB sockets, 1 micro
USB socket for OTG and another for power in, HDMI, SATA, 5V power for
SATA devices, gigabit Ethernet, an IR receiver, 3.5mm audio out and a
MIPI camera
On Sun, Feb 1, 2015 at 3:20 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Wed, Jan 28, 2015 at 03:54:12AM +0800, Chen-Yu Tsai wrote:
Some SoCs have a total of 4 possible USB controllers. One such example
is the A80, which has one USB3 dual role device and 3 EHCI/OHCI pairs.
Add
Am 31.01.2015, 11:50 Uhr, schrieb Maxime Ripard
maxime.rip...@free-electrons.com:
On Sat, Jan 31, 2015 at 09:49:36AM +0100, Irgendeiner wrote:
Am 29.01.2015, 21:45 Uhr, schrieb Maxime Ripard
maxime.rip...@free-electrons.com:
On Thu, Jan 29, 2015 at 09:37:25AM -0500, Stefan Monnier wrote:
Hello.
It seems that your device uses non-standard good block ratio that is not
supported by sunxi nand driver. Does it work on sdk lichee kernel?
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