Hi Thierry,
On Fri, Oct 30, 2015 at 06:32:30PM +0100, Thierry Reding wrote:
> On Fri, Oct 30, 2015 at 03:20:53PM +0100, Maxime Ripard wrote:
> > Add support for the Olimex LCD-OLinuXino-4.3TS panel to the DRM simple
> > panel driver.
> >
> > It is a 480x272 panel connected through a 24-bits RGB
Hi,
On Sat, Oct 31, 2015 at 05:53:26PM +0800, Chen-Yu Tsai wrote:
> On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard
> wrote:
> > The TCON is a controller generating the timings to output videos signals,
> > acting like both a CRTC and an encoder.
> >
> > It has
On Mon, Nov 02, 2015 at 01:53:20PM +1100, Jonathan Liu wrote:
> > + ret = sun4i_tv_init(drm);
> > + if (ret) {
> > + dev_err(drm->dev, "Couldn't create our RGB output\n");
>
> RGB should be composite. Seems like a copy-paste error.
Good catch. Thanks!
Maxime
--
Maxime
On 21/09/2015 at 11:33:18 +0200, Boris Brezillon wrote :
> When requested by a user, the PWM is assigned a default period and polarity
> extracted from the DT, the platform data or statically set by the driver.
> Those default values are currently stored in the period and polarity
> fields of the
Hi Rob,
On Fri, Oct 30, 2015 at 11:40:03AM -0500, Rob Herring wrote:
> > +Display Engine Backend
> > +--
> > +
> > +The display engine backend exposes layers and sprites to the
> > +system. It's split into two components, the frontend and backend, the
> > +frontend doing
Hi Stephen,
Thanks for your feedback!
On Fri, Oct 30, 2015 at 02:29:02PM -0700, Stephen Boyd wrote:
> > +
> > + mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> > + if (!mux)
> [..]
> > + goto free_reset;
> > + }
> > +
> > + return;
> > +
> > +free_reset:
> > + kfree(reset_data);
>
Hi Chen-Yu,
On Fri, Oct 30, 2015 at 11:20:41PM +0800, Chen-Yu Tsai wrote:
> On Fri, Oct 30, 2015 at 10:21 PM, Maxime Ripard
> wrote:
> > The TV encoder is used to drive VGA and composite display.
> >
> > Enable it on the CHIP
>
> The commit message does not
ADC seems to be using ldo2 for reference voltage.
Signed-off-by: Priit Laes
---
arch/arm/boot/dts/sun4i-a10-gemei-g9.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
Gemei G9 has internal speakers and headphone jack. Audio switching
from internal speakers to headphones is automatically handled by
extra FT2012Q audio amplifier chip that works out of the box.
Signed-off-by: Priit Laes
---
Changes since v2:
- Dropped routing property.
Improvements to devicetree setup:
- Converted to use axp209 regulator nodes
- Fix invalid regulator for LRADC keys
- Enable audio codec node
Changes sinve v2:
- Dropped applied "Added IRQ configuration for bma250 accelerometer" patch
Changes since v1:
- Dropped NAND patch because driver is
Add regulator nodes for axp209 using the axp209.dtsi include.
Signed-off-by: Priit Laes
---
Changes in v3:
- Drop the ohci0 node. It's not needed.
Changes in v2:
- Add the ohci0 node.
arch/arm/boot/dts/sun4i-a10-gemei-g9.dts | 35
1 file
Gentoo is source based, rolling-release distro.
You need permanently compile something to be updated )
As for cpuburn-a7 - it is a really stress test.
For me it reliable, because in real world with real software(even in
Gentoo), i can't stress A20 as cpuburn-a7 can.
четверг, 5 ноября 2015
Hi,
On Sat, Oct 31, 2015 at 06:28:16PM +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard
> wrote:
> > The A10 SoCs and its relatives has a special clock controller to drive the
> > display engines (both frontend and backend).
Hi,
On Sat, Oct 31, 2015 at 06:19:59PM +0800, Chen-Yu Tsai wrote:
> > +#define SUN4I_A10_TCON_CH0_RESET_SHIFT 29
>
> This is sun5i specific.
>
> A10s manual says bit 30 is the LCD reset, while bit 29 is the TV
> encoder reset. A13/R8 don't mention TCON_CH0 clock. A10/A20 have no
> separate TV
14 matches
Mail list logo