On Thu, 2016-01-14 at 16:24 +0100, Maxime Ripard wrote:
> The A10 SoCs and its relatives has a special clock controller to drive the
> display engines (both frontend and backend), that have a lot in common with
> the clock to drive the first TCON channel.
>
> Add a driver to support both.
...
>
On Thu, 2016-01-14 at 16:24 +0100, Maxime Ripard wrote:
> The Allwinner A10 and subsequent SoCs share the same display pipeline, with
> variations in the number of controllers (1 or 2), or the presence or not of
> some output (HDMI, TV, VGA) or not.
>
> Add a driver with a limited set of features
Hi,
On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
wrote:
> The A10 SoCs and its relatives has a special clock controller to drive the
> display engines (both frontend and backend), that have a lot in common with
> the clock to drive the first TCON channel.
>
>
Hi,
On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
wrote:
> The TCON is a controller generating the timings to output videos signals,
> acting like both a CRTC and an encoder.
>
> It has two channels depending on the output, each channel being driven by
> its
On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
wrote:
> The DRAM gates control whether the image / display devices on the SoC have
> access to the DRAM clock or not.
>
> Enable it.
>
> Signed-off-by: Maxime Ripard
> ---
>
Hi,
On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
wrote:
> Enable the display and TCON (channel 0 and channel 1) clocks that are going
> to be needed to drive the display engine, tcon and TV encoders.
>
> Signed-off-by: Maxime Ripard
Le 08/01/2016 12:24, Andre Przywara a écrit :
> (resending to add linux-crypto, patches unchanged)
>
> Hi,
>
> these two patches provide a different approach to an issue I tried
> to fix lately [1].
> Instead of casting everything I now promote local types to size_t, so
> that the min3()
Hi,
On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
wrote:
> The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
> PLL7, clocked from a 3MHz oscillator, that drives the display related
> clocks (GPU, display engine, TCON, etc.)
>
> Add a
Cubietruck Plus is a A83T/H8 based development board. The board has
standard DDR3 SDRAM, AXP818 PMIC/codec, SD/MMC, eMMC, USB 2.0 host
via HSIC USB Hub, USB OTG, SATA via USB bridge, gigabit ethernet,
WiFi, headphone out / mic in, and various GPIO headers.
The board also has an EEPROM on i2c0
The A83T, like previous Allwinner SoCs, has a watchdog as part of its
timer block. Add a device node for it.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
Hi Maxime,
This small series adds the timer/watchdog block for A83T, and also a new
board, the A83T/H8 based Cubietruck Plus from Cubietech.
Patch 1 from Vishnu adds the timer device node. This was picked from his
github branch sunxi-a83-wip.
Patch 2 adds the watchdog device node. We get
From: Vishnu Patekar
A83T timer is compatible with that of earlier SOCs.
Just add timer node to enable and re-use it.
Signed-off-by: Vishnu Patekar
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 8
On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
wrote:
> It turns out that the A13 / R8 also have a tve encoder block, and a gate
> for it.
>
> Add it to the DT.
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
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