Hi,
On Thu, Jan 28, 2016 at 1:49 AM, Maxime Ripard
wrote:
> On Mon, Jan 25, 2016 at 09:15:47PM +0800, Chen-Yu Tsai wrote:
>> sun8i-a23-mbus-clk used sunxi's factors clk, which is nice for very
>> complicated clocks, but is not really needed here.
>>
>> Convert
Hi,
On Wed, Jan 27, 2016 at 3:46 PM, Jean-Francois Moine wrote:
> Hi Jens,
>
> My H3 machine (OPI2) cannot boot with the PLL6 (periph0) as defined
> in the kernel 4.5-rc1. As there is no UART, I don't know what is wrong.
>
> But, applying your old patch
>
> [PATCH v4 1/6] clk:
On Mon, Jan 25, 2016 at 09:15:38PM +0800, Chen-Yu Tsai wrote:
> struct clk_factors_config contains shifts/widths for the factors of
> the factors clk. This is used to read out the factors from the register
> value. In no case is it written to, so make it const.
>
> Signed-off-by: Chen-Yu Tsai
On Mon, Jan 25, 2016 at 09:15:41PM +0800, Chen-Yu Tsai wrote:
> sunxi_factors_clk_setup() does not unmap registers when
> sunxi_factors_register() fails.
>
> This patch adds proper error handling, and also an error message
> when sunxi_factors_register() fails. Also use the full DT node name
> in
On Wed, 27 Jan 2016 15:36:21 +0100
Jens Kuske wrote:
> That sounds strange, 4.5-rc1 is working perfectly fine for me too.
>
> I doubt the patch you linked is responsible for making it work, it only
> removes the hardcoded output-names. If your DT isn't messed up this
>
On Sat, Jan 23, 2016 at 04:18:16PM +0100, codekip...@gmail.com wrote:
> From: Marcus Cooper
>
> Hi All,
>
> this patch series is an extension of the initial patch delivery for the
> Itead Ibox as found here
>
On Mon, Jan 25, 2016 at 09:15:40PM +0800, Chen-Yu Tsai wrote:
> sunxi's factors clk did not have an unregister function. This means
> multiple structs were leaked whenever a factors clk was unregistered.
>
> Add an unregister function for it. Also keep pointers to the mux and
> gate structs so
On 01/14, Maxime Ripard wrote:
> From: Matthias Brugger
>
> Some devices like SoCs from Mediatek need to use the clock
> through a regmap interface.
> This patch adds regmap support for the simple multiplexer clock,
> the divider clock and the clock gate code.
>
>
On Mon, Jan 25, 2016 at 09:15:45PM +0800, Chen-Yu Tsai wrote:
> The factors clk implementation has been extended to support custom
> recalc callbacks to support clocks that use one factor for certain
> parents only, like a pre-divider.
>
> Signed-off-by: Chen-Yu Tsai
Applied,
On Mon, Jan 25, 2016 at 09:15:47PM +0800, Chen-Yu Tsai wrote:
> sun8i-a23-mbus-clk used sunxi's factors clk, which is nice for very
> complicated clocks, but is not really needed here.
>
> Convert sun8i-a23-mbus-clk to use clk_composite, as it is a gate + mux
> + divider. This makes the code
On Mon, Jan 25, 2016 at 09:15:43PM +0800, Chen-Yu Tsai wrote:
> Some clocks cannot be modelled using the standard factors clk formula,
> such as clocks with special pre-dividers on one parent, or clocks
> with all power-of-two dividers.
>
> Add support for a custom .recalc callback for factors
Hi,
On 27-01-16 17:55, Jean-Francois Moine wrote:
On Wed, 27 Jan 2016 15:36:21 +0100
Jens Kuske wrote:
That sounds strange, 4.5-rc1 is working perfectly fine for me too.
I doubt the patch you linked is responsible for making it work, it only
removes the hardcoded
On Mon, Jan 25, 2016 at 09:15:42PM +0800, Chen-Yu Tsai wrote:
> The .get_factors callback of factors_clk has 6 parameters. To extend
> factors_clk in any way that requires adding parameters to .get_factors
> would make that list even longer, not to mention changing all the
> function declarations.
On Mon, Jan 25, 2016 at 09:15:44PM +0800, Chen-Yu Tsai wrote:
> The common clock framework requires either determine_rate or round_rate
> to be implemented. We use determine_rate so we can pass the parent index
> to the get_factors callback. This cannot be done easily with round_rate,
> so just
On Mon, Jan 25, 2016 at 09:15:46PM +0800, Chen-Yu Tsai wrote:
> sun6i's AR100 clock is a classic factors clk case:
>
> AR100 = ((parent mux) >> p) / (m + 1)
>
> Signed-off-by: Chen-Yu Tsai
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and
On Wed, Jan 27, 2016 at 04:52:10PM +0100, Maxime Ripard wrote:
> On Mon, Jan 25, 2016 at 09:15:40PM +0800, Chen-Yu Tsai wrote:
> > sunxi's factors clk did not have an unregister function. This means
> > multiple structs were leaked whenever a factors clk was unregistered.
> >
> > Add an
On Wed, 27 Jan 2016 19:16:42 +0100
Hans de Goede wrote:
> > To be sure, I generated a pure 4.5-rc1 kernel. Same result: no UART.
> > Maybe... one more information: I am using Allwinner's u-boot.
>
> Could be that that is the culprit, why are you not using upstream u-boot?
>
Hi Chen-Yu,
On Mon, Jan 25, 2016 at 09:15:36PM +0800, Chen-Yu Tsai wrote:
> Hi everyone,
>
> This series cleans up and reworks parts of sunxi's factors clk. The goal
> is to support non-standard formulas for clock rate calculation, such as
> pre-dividers on some parents, or all power-of-2
On Wed, Jan 27, 2016 at 02:51:13PM +0100, Jens Kuske wrote:
> GENMASK is inclusive on both ends, therefor one has to be
> subtracted from the width.
> Also fixes the mask for debug output.
>
> Signed-off-by: Jens Kuske
Applied, thanks!
Maxime
--
Maxime Ripard, Free
On Wed, 27 Jan 2016 16:18:53 +0800
Chen-Yu Tsai wrote:
> Hi,
Hi ChenYu,
> On Wed, Jan 27, 2016 at 3:46 PM, Jean-Francois Moine wrote:
> > Hi Jens,
> >
> > My H3 machine (OPI2) cannot boot with the PLL6 (periph0) as defined
> > in the kernel 4.5-rc1. As there is
On the A83T and H3, the SID block is at a different address.
Furthurmore, the e-fuses are at an offset of 0x200 within the
hardware's address space.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 7 +++
1 file changed, 7 insertions(+)
diff
GENMASK is inclusive on both ends, therefor one has to be
subtracted from the width.
Also fixes the mask for debug output.
Signed-off-by: Jens Kuske
---
drivers/soc/sunxi/sunxi_sram.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
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