On 05/01/17 17:57, Maxime Ripard wrote:
> Hi Rob,
>
> On Wed, Jan 04, 2017 at 08:07:50AM -0600, Rob Herring wrote:
>> On Mon, Jan 02, 2017 at 11:03:43PM +, Andre Przywara wrote:
>>> From: Maxime Ripard
>>>
>>> Unlike the A64 user manual reports, the third
On Fri, Dec 30, 2016 at 01:55:44PM +0100, Linus Walleij wrote:
> On Mon, Dec 26, 2016 at 3:33 PM, André Przywara
> wrote:
>
> > So while this patch technically looks correct, I was wondering if we
> > should really explore the possibility of making the whole of sunxi
> >
On Thu, Dec 29, 2016 at 03:01:01AM +0800, Icenowy Zheng wrote:
> V3s devices won't have enough memory to load U-Boot binary at
> 0x4a00, and they do not have enough memory to reserve 64MiB for
> malloc() (it has only 64MiB at all!)
> Change the text base to 0x4100, and cut down malloc()
On Thu, Dec 29, 2016 at 03:00:58AM +0800, Icenowy Zheng wrote:
> H3-like DRAM controller needs some special code to operate a DDR2 DRAM
> chip. Add the logic to probe such a chip.
>
> As there's no commercial boards available now with H3 and DDR2 DRAM, the
> patch is developed and tested on a V3s
On Thu, Dec 29, 2016 at 02:50:49AM +0800, Icenowy Zheng wrote:
> From: Andre Przywara
>
> According to Jens disabling the on-die-termination should set bit 5,
> not bit 1 in the respective register. Fix this.
>
> Reported-by: Jens Kuske
>
On Tue, Dec 27, 2016 at 01:11:56AM +0800, Icenowy Zheng wrote:
> From: Andre Przywara
>
> The Orange Pi PC 2 is a typical single board computer using the
> Allwinner H5 SoC. Apart from the usual suspects it features three
> separately driven USB ports and a Gigabit
On Tue, Dec 27, 2016 at 12:25:13AM +0800, Icenowy Zheng wrote:
> Based on the Allwinner H5 datasheet and the pinctrl driver of the
> backward-compatible H3 this introduces the pin multiplex assignments for
> the H5 SoC.
>
> H5 introduced some more pin functions (e.g. three more groups of TS
>
On Tue, Dec 27, 2016 at 12:25:15AM +0800, Icenowy Zheng wrote:
> Add the H5 CCU clocks set based on the H3 one.
>
> Signed-off-by: Icenowy Zheng
Is there any difference with H3's?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
On Fri, Dec 23, 2016 at 09:09:27PM +0800, Icenowy Zheng wrote:
> Lichee Pi One is a low-cost Allwinner A13 based development board, with
> two SD slots, a USB2.0 OTG port, a USB2.0 host port (or onboard Wi-Fi
> card), optional headers for LCD and CSI and two GPIO headers.
>
> Add support for this
On Fri, Dec 23, 2016 at 04:31:33PM +0800, Icenowy Zheng wrote:
> Pine64+ uses DLDO4 for wireless network, and DC1SW for wired network.
>
> Enable these two regulators, in order to provide net support in U-Boot
> and Linux.
>
> Signed-off-by: Icenowy Zheng
> ---
>
On Fri, Dec 23, 2016 at 04:31:32PM +0800, Icenowy Zheng wrote:
> The A64 uses the AXP803 as its PMIC.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm/mach-sunxi/Makefile | 3 +
> arch/arm/mach-sunxi/pmic_bus.c | 6 +-
> arch/arm/mach-sunxi/rsb.c | 2 +-
>
Hi Rob,
On Wed, Jan 04, 2017 at 08:07:50AM -0600, Rob Herring wrote:
> On Mon, Jan 02, 2017 at 11:03:43PM +, Andre Przywara wrote:
> > From: Maxime Ripard
> >
> > Unlike the A64 user manual reports, the third MMC controller on the
> > A64 (and the only one
On Mon, Jan 02, 2017 at 11:03:44PM +, Andre Przywara wrote:
> Signed-off-by: Andre Przywara
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 67
> +++
> 1 file changed, 67 insertions(+)
>
> diff --git
Hi,
On Mon, Jan 02, 2017 at 11:03:42PM +, Andre Przywara wrote:
> The calibration facility in the A64 MMC block seems to have been
> misunderstood: the result value is not the value to program into the
> delay bits, but is the number of delay cells that result in a full clock
> cycle delay.
On Mon, Jan 02, 2017 at 11:03:46PM +, Andre Przywara wrote:
> The Banana Pi M64 board is a typical single board computer based on the
> Allwinner A64 SoC. Aside from the usual peripherals it features eMMC
> storage, which is connected to the 8-bit capable SDHC2 controller.
> Also it has a
On Thu, 05 Jan 2017, Chen-Yu Tsai wrote:
> The AXP806 supports either master/standalone or slave mode.
> Slave mode allows sharing the serial bus, even with multiple
> AXP806 which all have the same hardware address.
>
> This is done with extra "serial interface address extension",
> or
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