On Fri, Jan 13, 2017 at 01:30:01AM +, Andre Przywara wrote:
> For the arch timer to work properly, we need to setup the CNTFRQ
> register, which is only possible in EL3.
> Define the arch timer frequency in sun8i.h as well, so that ARMv8's
> start.S can program the register correctly.
>
> Sign
On Fri, Jan 13, 2017 at 09:42:28AM +, Andre Przywara wrote:
> > Re wanting to build SPL either as 32-bit or 64-bit, could this be a
> > Kconfig option perhaps?
>
> Sounds like a direction worth to investigate.
> In the moment we have two separate defconfig files, because CPU_V7 and
> ARM64 are
On 16/01/17 08:55, Maxime Ripard wrote:
> On Fri, Jan 13, 2017 at 09:42:28AM +, Andre Przywara wrote:
>>> Re wanting to build SPL either as 32-bit or 64-bit, could this be a
>>> Kconfig option perhaps?
>>
>> Sounds like a direction worth to investigate.
>> In the moment we have two separate def
On Mon, Jan 16, 2017 at 09:47:06AM +, André Przywara wrote:
> On 16/01/17 08:55, Maxime Ripard wrote:
> > On Fri, Jan 13, 2017 at 09:42:28AM +, Andre Przywara wrote:
> >>> Re wanting to build SPL either as 32-bit or 64-bit, could this be a
> >>> Kconfig option perhaps?
> >>
> >> Sounds like
On Mon, Jan 09, 2017 at 12:16:00AM +, André Przywara wrote:
> On 05/01/17 22:42, Maxime Ripard wrote:
> > On Fri, Dec 30, 2016 at 01:55:44PM +0100, Linus Walleij wrote:
> >> On Mon, Dec 26, 2016 at 3:33 PM, André Przywara
> >> wrote:
> >>
> >>> So while this patch technically looks correct, I
Hi Ondrej,
Sorry for the late reply,
On Mon, Jan 09, 2017 at 03:50:42PM +0100, Ondřej Jirman wrote:
> Dne 9.1.2017 v 10:59 Maxime Ripard napsal(a):
> > On Sat, Jan 07, 2017 at 04:49:18PM +0100, Ondřej Jirman wrote:
> >> Maxime,
> >>
> >> Dne 25.11.2016 v 01:28 meg...@megous.com napsal(a):
> >>> F
Hi Maxime,
Dne 16.1.2017 v 17:43 Maxime Ripard napsal(a):
>> It does lock up quickly with mainline ccu_nkmp_find_best algorithm
>> for finding factors.
>>
>> Even with linux kernel, it breaks. It's just more difficult to hit the
>> right conditions. I got oops only right after boot when running cp
Dne 16.1.2017 v 20:14 Icenowy Zheng napsal(a):
> The PHY0 on H3 can be wired either to MUSB controller or OHCI/EHCI
> controller.
>
> The original driver wired it to OHCI/EHCI controller; however, as the
> code to use PHY0 as OHCI/EHCI is missing, it makes the PHY fully
> unusable.
>
> Rename the
