Hi,
The problem I had was when copying and pasting the contents of the patch
into a file from the google groups website.
The patch failed. I found the option to "show the original message" and it
worked perfectly.
Thanks a lot,
Francisco.
El sábado, 21 de enero de 2017, 17:19:16 (UTC-3),
Hi,
On 16/01/17 07:44, Maxime Ripard wrote:
> On Fri, Jan 13, 2017 at 08:28:07AM +, André Przywara wrote:
>> On 13/01/17 08:09, Vishnu Patekar wrote:
>> Hi Vishnu,
>>
>>> Even for the single core cortex-a7, SMP bit should be set before
>>> enabling MMU and cache.
>>>
>>> Reference: Cortex A7
Hi,
On 16/01/17 08:01, Maxime Ripard wrote:
> On Fri, Jan 13, 2017 at 01:30:01AM +, Andre Przywara wrote:
>> For the arch timer to work properly, we need to setup the CNTFRQ
>> register, which is only possible in EL3.
>> Define the arch timer frequency in sun8i.h as well, so that ARMv8's
>>
On 16/01/17 07:59, Maxime Ripard wrote:
> On Fri, Jan 13, 2017 at 01:30:00AM +, Andre Przywara wrote:
>> The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores.
>> To allow sharing the clocks, GPIO and driver code easily, create an
>> architecture agnostic MACH_SUN8I_H3_H5 Kconfig
On Friday, January 20, 2017 at 10:08:41 PM UTC+1, Francisco Larramendi
wrote:
>
> Hi,
>
> I need to use this patch in a project.
> Where can I get this patch from in a form I can use?
>
> Regards
> Francisco Larramendi
>
>
Just save the contents of the post into .patch file and apply with patch
On Sat, 2017-01-21 at 18:06 +0100, Maxime Ripard wrote:
> On Sat, Jan 21, 2017 at 07:48:46AM +0200, Priit Laes wrote:
> > > > > > After cherry-picking and fixing the conflicts, it seems to
> > > > > > fix
> > > > > > booting
> > > > > > from the sdcard on 4.10-rc (or current mainline master).
> >
On Sat, Jan 21, 2017 at 07:48:46AM +0200, Priit Laes wrote:
> > > > > After cherry-picking and fixing the conflicts, it seems to fix
> > > > > booting
> > > > > from the sdcard on 4.10-rc (or current mainline master).
> > > >
> > > > This will severely conflict with what arm-soc already have
> >
A typo or copy-paste bug means that the register access intended for
regulator dcdce goes to dcdcb instead. This patch corrects it.
Signed-off-by: Rask Ingemann Lambertsen
Fixes: 2ca342d391e3 (regulator: axp20x: Support AXP806 variant)
---
I have a board where dcdcb powers
On 21/01/17 04:05, Siarhei Siamashka wrote:
Hi Siarhei,
thanks for your comments!
> On Fri, 20 Jan 2017 21:55:53 +
> André Przywara wrote:
>
>> On 20/01/17 21:35, Maxime Ripard wrote:
>>
>> Hi Maxime,
>>
>> thanks for having a look!
>>
>>> On Fri, Jan 20, 2017 at
On 21/01/17 04:24, Siarhei Siamashka wrote:
Hi Siarhei,
> On Fri, 20 Jan 2017 01:53:25 +
> Andre Przywara wrote:
>
>> mksunxiboot limits the size of the resulting SPL binaries to pretty
>> conservative values to cover all SoCs and all boot media (NAND).
>> In
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