[linux-sunxi] Re: [RFC PATCH 00/11] extend FIT loading support (plus Pine64/ATF support)

On 27/01/17 21:29, Simon Glass wrote: Hi Simon, > On 19 January 2017 at 18:53, Andre Przywara wrote: >> Currently the FIT format is not used to its full potential in the SPL: >> It only loads the first image from the /images node and appends the >> proper FDT. >> Some

[linux-sunxi] Re: [RFC PATCH 01/11] SPL: FIT: refactor FDT loading

On 27/01/17 21:29, Simon Glass wrote: > Hi Andre, > > On 19 January 2017 at 18:53, Andre Przywara wrote: >> >> Currently the SPL FIT loader uses the spl_fit_select_fdt() function to >> find the offset to the right DTB within the FIT image. >> For this it iterates over all

[linux-sunxi] Re: [RFC PATCH 02/11] SPL: FIT: rework U-Boot image loading

On 19 January 2017 at 18:53, Andre Przywara wrote: > Currently the SPL FIT loader always looks only for the first image in > the /images node a FIT tree, which it loads and later executes. > > Generalize this by looking for a "firmware" property in the matched >

[linux-sunxi] Re: [RFC PATCH 00/11] extend FIT loading support (plus Pine64/ATF support)

Hi Andre, On 19 January 2017 at 18:53, Andre Przywara wrote: > Currently the FIT format is not used to its full potential in the SPL: > It only loads the first image from the /images node and appends the > proper FDT. > Some boards and platforms would benefit from loading

[linux-sunxi] Re: [RFC PATCH 01/11] SPL: FIT: refactor FDT loading

Hi Andre, On 19 January 2017 at 18:53, Andre Przywara wrote: > > Currently the SPL FIT loader uses the spl_fit_select_fdt() function to > find the offset to the right DTB within the FIT image. > For this it iterates over all subnodes of the /configuration node in > the

[linux-sunxi] Re: [PATCH 06/11] clk: sunxi-ng: Add A80 USB CCU

On Tue, Jan 24, 2017 at 10:32:25AM +0800, Chen-Yu Tsai wrote: > Add support for the USB clock controls found on the A80. > > Signed-off-by: Chen-Yu Tsai > --- > .../devicetree/bindings/clock/sun9i-usb.txt| 24 > drivers/clk/sunxi-ng/Makefile |

[linux-sunxi] Re: [PATCH 05/11] clk: sunxi-ng: Add A80 CCU

On Tue, Jan 24, 2017 at 10:32:24AM +0800, Chen-Yu Tsai wrote: > Add support for the main clock unit found in the A80. > > Note that on the A80, some subsystems have separate clock controllers > downstream of the main clock unit. These include the MMC, USB, and > display engine subsystems. > >

Re: [linux-sunxi] Re: [PATCH v2 4/9] arm: dts: sun8i: split Allwinner H3 .dtsi

On Sat, Jan 28, 2017 at 12:02:20AM +0800, Icenowy Zheng wrote: > > 2017年1月27日 23:55于 Maxime Ripard 写道： > > > > On Thu, Jan 26, 2017 at 11:48:54PM +0800, Icenowy Zheng wrote: > > > - mmc0: mmc@01c0f000 { > > > + mmc@01c0f000 { > > > > There's no point in

Re: [linux-sunxi][PATCH 0/3] Enable SPDIF on the Beelink X2

On Fri, Jan 27, 2017 at 04:48:05PM +0100, codekip...@gmail.com wrote: > From: Marcus Cooper > > Hi All, > > here is the patchset required to get SPDIF working on the Beelink X2 > which is a H3 based STB. > > BR, > CK Merged all three, but this could have been in your

[linux-sunxi] Re: [PATCH v2 8/9] ASoC: sunxi: allow the analog codec driver to be built on ARM64

On Thu, Jan 26, 2017 at 11:48:58PM +0800, Icenowy Zheng wrote: > As the 64-bit Allwinner H5 SoC has the same analog codec part (also the > same digital part) as H3, enable the driver to be built on ARM64 > Allwinner platform, so that it can be used on H5. > > Signed-off-by: Icenowy Zheng

[linux-sunxi] Whither the DRM driver for A20?

I was very happy several months ago to see a preliminary patch that added a DRM driver for the A10/A20. But when I look at http://linux-sunxi.org/Linux_mainlining_effort the status of DRM support for A20 says "Nobody works on it, but it should be compatible with already done drivers". Oddly

[linux-sunxi] Re: [PATCH v2 7/9] dmaengine: sun6i: allow build on ARM64 platforms (sun50i)

On Thu, Jan 26, 2017 at 11:48:57PM +0800, Icenowy Zheng wrote: > As 64-bot Allwinner H5 SoC has the same DMA engine with H3, the DMA > driver should be allowed to be built for ARM64, in order to make it work on > H5. > > Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard

[linux-sunxi] Re: [PATCH v2 6/9] arm64: dts: allwinner: add Allwinner H5 .dtsi

On Thu, Jan 26, 2017 at 11:48:56PM +0800, Icenowy Zheng wrote: > + mmc@01c0f000 { Please use a label based syntax here too. > + compatible = "allwinner,sun50i-a64-mmc", > + "allwinner,sun5i-a13-mmc"; The compatibility with the A13

[linux-sunxi] Re: [PATCH v2 4/9] arm: dts: sun8i: split Allwinner H3 .dtsi

On Thu, Jan 26, 2017 at 11:48:54PM +0800, Icenowy Zheng wrote: > - mmc0: mmc@01c0f000 { > + mmc@01c0f000 { There's no point in removing the labels, and you can even use the label-based syntax to reference them, instead of using the path. Maxime -- Maxime Ripard, Free

[linux-sunxi] Re: [PATCH v2 3/9] clk: sunxi-ng: add support for Allwinner H5 SoC

On Thu, Jan 26, 2017 at 11:48:53PM +0800, Icenowy Zheng wrote: > Allwinner H5 is a SoC that features a CCU like H3, but with MMC phase > clocks removed (for new MMC controller) and a new bus gate/reset > imported. > > Add support for it. > > Signed-off-by: Icenowy Zheng > ---

[linux-sunxi] Re: [PATCH v2 1/9] drivers: pinctrl: add driver for Allwinner H5 SoC

On Thu, Jan 26, 2017 at 11:48:51PM +0800, Icenowy Zheng wrote: > Based on the Allwinner H5 datasheet and the pinctrl driver of the > backward-compatible H3 this introduces the pin multiplex assignments for > the H5 SoC. > > H5 introduced some more pin functions (e.g. three more groups of TS >

[linux-sunxi][PATCH 3/3] ARM: dts: sun8i-h3: Add SPDIF to the Beelink X2

From: Marcus Cooper Enable the S/PDIF transmitter that is present on the Beelink X2 STB. Signed-off-by: Marcus Cooper --- arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 24 1 file changed, 24 insertions(+) diff --git

[linux-sunxi][PATCH 2/3] ARM: dts: sun8i-h3: Add the SPDIF block to the H3

From: Marcus Cooper Add the SPDIF transceiver controller block to the H3 dtsi. Signed-off-by: Marcus Cooper --- arch/arm/boot/dts/sun8i-h3.dtsi | 13 + 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi

[linux-sunxi][PATCH 1/3] ARM: dts: sun8i-h3: Add SPDIF TX pin to the H3

From: Marcus Cooper Add the SPDIF TX pin to the H3 dtsi. Signed-off-by: Marcus Cooper --- arch/arm/boot/dts/sun8i-h3.dtsi | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi

[linux-sunxi][PATCH 0/3] Enable SPDIF on the Beelink X2

From: Marcus Cooper Hi All, here is the patchset required to get SPDIF working on the Beelink X2 which is a H3 based STB. BR, CK Marcus Cooper (3): ARM: dts: sun8i-h3: Add SPDIF TX pin to the H3 ARM: dts: sun8i-h3: Add the SPDIF block to the H3 ARM: dts: sun8i-h3:

Re: [linux-sunxi][PATCH v3] ARM: dts: sun8i-h3: Add dts for the Beelink X2 STB

On Thu, Jan 26, 2017 at 08:48:04PM +0100, codekip...@gmail.com wrote: > From: Marcus Cooper > > The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot, > 2 USB ports( 1 * USB-2 Host, 1 USB OTG), a 10/100M ethernet port using the > SoC's integrated PHY, Wifi

[linux-sunxi] Re: [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU

On Fri, Jan 27, 2017 at 05:26:53PM +0800, Chen-Yu Tsai wrote: > On Fri, Jan 27, 2017 at 4:58 PM, Maxime Ripard > wrote: > > On Thu, Jan 26, 2017 at 07:20:22PM +0800, Chen-Yu Tsai wrote: > >> On Thu, Jan 26, 2017 at 6:39 PM, Maxime Ripard > >>

[linux-sunxi] Re: [PATCH 1/2] nvmem: sunxi-sid: add support for H3 and A64's SID controller

On Fri, Jan 27, 2017 at 05:26:59PM +0800, Icenowy Zheng wrote: > > > +Example for sun8i-h3: > > > + sid@01c14000 { > > > + compatible = "allwinner,sun8i-h3-sid"; > > > + /* > > > + * The length of SID on H3 is 0x100 bytes, add the value offset > > > + * 0x200, so the total length should be

[linux-sunxi] Re: [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU

On Fri, Jan 27, 2017 at 4:58 PM, Maxime Ripard wrote: > On Thu, Jan 26, 2017 at 07:20:22PM +0800, Chen-Yu Tsai wrote: >> On Thu, Jan 26, 2017 at 6:39 PM, Maxime Ripard >> wrote: >> > Hi, >> > >> > On Tue, Jan 24, 2017 at

[linux-sunxi] Re: [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU

On Thu, Jan 26, 2017 at 07:20:22PM +0800, Chen-Yu Tsai wrote: > On Thu, Jan 26, 2017 at 6:39 PM, Maxime Ripard > wrote: > > Hi, > > > > On Tue, Jan 24, 2017 at 10:32:26AM +0800, Chen-Yu Tsai wrote: > >> Add support for the display engine clock controls found on

Re: [linux-sunxi] Re: [PATCH 1/2] nvmem: sunxi-sid: add support for H3 and A64's SID controller

Hi Maxime, On Fri, Jan 27, 2017 at 7:17 PM, Maxime Ripard wrote: > Hi, > > On Thu, Jan 26, 2017 at 07:33:44PM +0800, Icenowy Zheng wrote: >> H3 and A64 SoCs have a bigger SID controller, which has its direct read >> address at 0x200 position in the SID block,

[linux-sunxi] Re: [PATCH 10/11] arm64: dts: allwinner: Remove no longer used pinctrl/sun4i-a10.h header

On Thu, Jan 26, 2017 at 07:23:25PM +0800, Chen-Yu Tsai wrote: > On Thu, Jan 26, 2017 at 6:15 PM, Maxime Ripard > wrote: > > On Tue, Jan 24, 2017 at 10:32:29AM +0800, Chen-Yu Tsai wrote: > >> All dts files for the sunxi platform have been switched to the generic >

Re: [linux-sunxi] Re: [PATCH 06/11] clk: sunxi-ng: Add A80 USB CCU

On Thu, Jan 26, 2017 at 07:12:44PM +0800, Chen-Yu Tsai wrote: > On Thu, Jan 26, 2017 at 6:14 PM, Maxime Ripard > wrote: > > Hi, > > > > On Tue, Jan 24, 2017 at 10:32:25AM +0800, Chen-Yu Tsai wrote: > >> Add support for the USB clock controls found on the A80. >

[linux-sunxi] Re: [PATCH 1/2] nvmem: sunxi-sid: add support for H3 and A64's SID controller

Hi, On Thu, Jan 26, 2017 at 07:33:44PM +0800, Icenowy Zheng wrote: > H3 and A64 SoCs have a bigger SID controller, which has its direct read > address at 0x200 position in the SID block, not 0x0. > > Also, H3 SID controller has some silicon bug that makes the direct read > value wrong at first,