On Tue, Feb 07, 2017 at 05:08:16AM +0800, Icenowy Zheng wrote:
>
> 2017年2月7日 03:14于 Jelle van der Waa 写道:
> >
> > add support for the NanoPi NEO Air H3 board from friendlyarm.com . This
> > board contains WiFi, Bluetooth, 8GB eMMC storage and 512 MB DDR3 ram.
>
> Is
On Sat, Feb 4, 2017 at 10:55 PM, wrote:
> From: Siarhei Volkau
>
> A31 SoC have a different map of PWM registers than others Allwinner
> SoCs, so the operation of access to the registers reworked for all
> existing in driver SoCs.
>
> Tested on Onda V972
On Tue, Feb 7, 2017 at 5:08 AM, Icenowy Zheng wrote:
>
> 2017年2月7日 03:14于 Jelle van der Waa 写道:
>>
>> add support for the NanoPi NEO Air H3 board from friendlyarm.com . This
>> board contains WiFi, Bluetooth, 8GB eMMC storage and 512 MB DDR3 ram.
>
> Is
add support for the NanoPi NEO Air H3 board from friendlyarm.com . This
board contains WiFi, Bluetooth, 8GB eMMC storage and 512 MB DDR3 ram.
Signed-off-by: Jelle van der Waa
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
Hi Andrew,
On 06/02/17 16:17, Andrew F. Davis wrote:
> On 02/06/2017 09:33 AM, Simon Glass wrote:
>> Hi Andre,
>>
>> On 27 January 2017 at 17:47, André Przywara wrote:
>>> On 27/01/17 21:29, Simon Glass wrote:
>>>
>>> Hi Simon,
>>>
On 19 January 2017 at 18:53, Andre
Hi Simon,
On 06/02/17 15:33, Simon Glass wrote:
> Hi Andre,
>
> On 27 January 2017 at 17:47, André Przywara wrote:
>> On 27/01/17 21:29, Simon Glass wrote:
>>
>> Hi Simon,
>>
>>> On 19 January 2017 at 18:53, Andre Przywara wrote:
Currently
Hi Andre,
On 27 January 2017 at 17:47, André Przywara wrote:
> On 27/01/17 21:29, Simon Glass wrote:
>
> Hi Simon,
>
>> On 19 January 2017 at 18:53, Andre Przywara wrote:
>>> Currently the FIT format is not used to its full potential in the SPL:
Hi,
On 03/02/17 10:52, Jagan Teki wrote:
> On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara wrote:
>> Instead of enumerating all SoC families that need that bit set, let's
>> just express this more clearly: The SMP bits needs to be set on
>> SMP capable ARMv7 CPUs. It's
Hi,
On 03/02/17 11:14, Jagan Teki wrote:
> On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara wrote:
>> The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
>> Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi
>> and changing the differing
Hi,
Chen-Yu, thanks for your comments.
On 03/02/17 16:36, Chen-Yu Tsai wrote:
> Hi,
>
> On Fri, Feb 3, 2017 at 11:26 PM, Jagan Teki wrote:
>> On Feb 1, 2017 2:37 AM, "Andre Przywara" wrote:
>>
>> The DRAM controller in the Allwinner H5 SoC is again
On Thu, Feb 02, 2017 at 09:13:37PM +0800, Icenowy Zheng wrote:
> The H3 SoC have a bigger SID controller, which has its direct read
> address at 0x200 position in the SID block, not 0x0.
>
> Also, H3 SID controller has some silicon bug that makes the direct read
> value wrong at cold boot, add
On Thu, Feb 02, 2017 at 09:13:36PM +0800, Icenowy Zheng wrote:
> Sometimes the SID device have more memory address space than the real
> NVMEM size (for the registers used to read/write the SID).
>
> Fetch the NVMEM size from device compatible, rather than the memory
> address space's length, in
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