On Fri, Jun 30, 2017 at 5:19 AM, Rob Herring wrote:
> On Tue, Jun 27, 2017 at 07:07:34PM +0800, Yong Deng wrote:
>> Add binding documentation for Allwinner CSI.
>
> For the subject:
>
> dt-bindings: media: Add Allwinner Camera Sensor Interface (CSI)
>
> "binding documentation" is
On Fri, Jun 30, 2017 at 6:22 AM, Jonathan Liu wrote:
> Hi Maxime,
>
> On 30 June 2017 at 01:56, Maxime Ripard
> wrote:
>> On Wed, Jun 28, 2017 at 08:39:33PM +1000, Jonathan Liu wrote:
>>> >> + u32 int_status;
>>> >> + u32 fifo_status;
Hi Maxime,
On 30 June 2017 at 01:56, Maxime Ripard
wrote:
> On Wed, Jun 28, 2017 at 08:39:33PM +1000, Jonathan Liu wrote:
>> >> + u32 int_status;
>> >> + u32 fifo_status;
>> >> + /* Read needs empty flag unset, write needs full flag unset */
>> >> +
On Tue, Jun 27, 2017 at 07:07:34PM +0800, Yong Deng wrote:
> Add binding documentation for Allwinner CSI.
For the subject:
dt-bindings: media: Add Allwinner Camera Sensor Interface (CSI)
"binding documentation" is redundant.
>
> Signed-off-by: Yong Deng
> ---
>
From: Corentin Labbe
Date: Thu, 29 Jun 2017 19:02:38 +0200
> On Thu, Jun 29, 2017 at 12:23:49PM -0400, David Miller wrote:
>> From: Corentin Labbe
>> Date: Tue, 27 Jun 2017 11:28:01 +0200
>>
>> > The current way to find if the phy is
On Thu, Jun 29, 2017 at 12:23:49PM -0400, David Miller wrote:
> From: Corentin Labbe
> Date: Tue, 27 Jun 2017 11:28:01 +0200
>
> > The current way to find if the phy is internal is to compare DT phy-mode
> > and emac_variant/internal_phy.
> > But it will negate a
在 2017-06-30 00:23,David Miller 写道:
From: Corentin Labbe
Date: Tue, 27 Jun 2017 11:28:01 +0200
The current way to find if the phy is internal is to compare DT
phy-mode
and emac_variant/internal_phy.
But it will negate a possible future SoC where an external PHY use
From: Corentin Labbe
Date: Tue, 27 Jun 2017 11:28:01 +0200
> The current way to find if the phy is internal is to compare DT phy-mode
> and emac_variant/internal_phy.
> But it will negate a possible future SoC where an external PHY use the
> same phy mode than the
Hi,
On Wed, Jun 28, 2017 at 08:52:24PM +1000, Jonathan Liu wrote:
> The documentation for drm_do_get_edid in drivers/gpu/drm/drm_edid.c states:
> "As in the general case the DDC bus is accessible by the kernel at the I2C
> level, drivers must make all reasonable efforts to expose it as an I2C
>
On Wed, Jun 28, 2017 at 08:39:33PM +1000, Jonathan Liu wrote:
> >> + u32 int_status;
> >> + u32 fifo_status;
> >> + /* Read needs empty flag unset, write needs full flag unset */
> >> + u32 flag = read ? SUN4I_HDMI_DDC_FIFO_STATUS_EMPTY :
> >> +
But actually in the megous fork I see thermal zones for H5
Il giorno giovedì 29 giugno 2017 16:12:39 UTC+2, ice...@aosc.io ha scritto:
>
> 在 2017-06-28 18:07,Menion 写道:
> > Hi all
> > Googling a little bit, I have found reference to a series of 5 patches
> > Icenowy Zheng provided for adding
在 2017-06-28 19:40,Menion 写道:
Hi
Thanks for having pointed it out
Do you know if there is a specific reason, why the cpufreq, according
to the Sunxi mainlining effort, is not even in any plan for 4.13
Kernel?
Just no one is doing it.
Bye
Il giorno mercoledì 28 giugno 2017 13:01:27 UTC+2,
在 2017-06-28 18:07,Menion 写道:
Hi all
Googling a little bit, I have found reference to a series of 5 patches
Icenowy Zheng provided for adding cpufreq support to H5 cores
But I can only find the 3/5 patch. Moreover it seems that they didn't
go in the mainline, still the 4.12RC is not including
HI All,
I am newbie here, I have a A33 tablet came with android I am trying to
get linux on it.
I could boot linux from SD card , now I want to boot from NAND but when
i look for /dev/nand it is not available instead i get (result of lsblk)
/dev/nanda
/dev/nandb
/dev/nandc
2017-06-29 15:53 GMT+08:00 Maxime Ripard :
> On Thu, Jun 29, 2017 at 12:45:51PM +0800, Ziping Chen wrote:
>> 2017-06-28 1:36 GMT+08:00 Maxime Ripard :
>> > Hi,
>> >
>> > On Tue, Jun 27, 2017 at 11:29:10PM +0800, icen...@aosc.io
On Thu, Jun 29, 2017 at 01:28:12PM +0200, Emmanuel Vadot wrote:
> On Thu, 29 Jun 2017 11:57:05 +0100
> Andre Przywara wrote:
>
> > Hi,
> >
> > On 25/06/17 21:45, Priit Laes wrote:
> > > Convert sun7i-a20.dtsi to new CCU driver.
> >
> > I know that some people hat^Wget
On Thu, Jun 29, 2017 at 11:57:05AM +0100, Andre Przywara wrote:
> Hi,
>
> On 25/06/17 21:45, Priit Laes wrote:
> > Convert sun7i-a20.dtsi to new CCU driver.
>
> I know that some people hat^Wget annoyed by me asking this, but anyway:
>
> Why do we actually need this?
>
> This ultimately makes
Hi,
On 25/06/17 21:45, Priit Laes wrote:
> Convert sun7i-a20.dtsi to new CCU driver.
I know that some people hat^Wget annoyed by me asking this, but anyway:
Why do we actually need this?
This ultimately makes the DT incompatible with older kernels (as
actually shipped by distros today).
So if
On Thu, Jun 29, 2017 at 12:45:51PM +0800, Ziping Chen wrote:
> 2017-06-28 1:36 GMT+08:00 Maxime Ripard :
> > Hi,
> >
> > On Tue, Jun 27, 2017 at 11:29:10PM +0800, icen...@aosc.io wrote:
> >> Maxime, here's another problem: if we have already a GP LRADC driver,
>
Hi,
On Thu, Jun 29, 2017 at 12:35:30PM +0800, Ziping Chen wrote:
> 2017-06-28 1:31 GMT+08:00 Maxime Ripard :
> > On Tue, Jun 27, 2017 at 11:18:17PM +0800, Ziping Chen wrote:
> >> 2017-06-27 1:15 GMT+08:00 Maxime Ripard :
> >> >
On Wed, Jun 28, 2017 at 05:59:49PM +, Priit Laes wrote:
> On Tue, Jun 27, 2017 at 11:46:07AM +0200, Maxime Ripard wrote:
> > Hi!
> >
> > On Sun, Jun 25, 2017 at 11:45:42PM +0300, Priit Laes wrote:
> > > SATA clock on sun4i/sun7i is of type (parent) / M / 6 where
> > > 6 is fixed post-divider.
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