The A83T has 3 USB PHYs, 1 for OTG, 1 for standard USB, 1 for USB HSIC.
The phy initialization procedure is very different from other SoCs, but
the PMU bits are the same, with additional bits for HSIC.
Signed-off-by: Chen-Yu Tsai
Tested-by: Maxime Ripard
---
drivers/phy/allwinner/phy-sun4i-usb.
The Allwinner H3 SoC has 4 USB PHYs, so it needs four sets of pmu
regions, clocks, resets, and optional vbus properties. These were
not described when the H3 compatible string was added.
Fixes: 626a630e003c ("phy-sun4i-usb: Add support for the host usb-phys
found on the H3 So
The A83T has 3 USB PHYs, 1 for USB OTG, 1 for standard USB 2.0, 1 for
USB HSIC. EHCI0/OHCI0 are the standard USB host pair, while EHCI1 is
the host controller for HSIC. OTG is not added yet.
Signed-off-by: Chen-Yu Tsai
Tested-by: Maxime Ripard
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 62
The USB OTG controller found on the A83T is compatible with the one
found on the A33.
Add a device node for it.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boo
On the Allwinner A83T SoC, the last USB PHY is an HSIC PHY. It requires
two clocks instead of one.
On all Allwinner SoCs that share the common USB PHY design supported by
the phy-sun4i-usb driver, the first PHY is always tied to OTG, and there
is at most one HSIC PHY, typically the last.
In this
Hi everyone,
This series enables USB host support for the Allwinner A83T SoC.
The A83T's USB OTG PHY uses different controls. The USB 2.0 host
PHYs are the same as previous chips. And the HSIC part is actually
used on some boards.
The external bits needed for proper USB OTG support is not there
y
The h8homlet board has the A83T's standard USB 1.1/2.0 host pair routed
to a USB host port on the board. The other USB host port is routed to
USB OTG controller.
Signed-off-by: Chen-Yu Tsai
---
.../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 29 ++
1 file changed, 29 ins
The A83T has 3 USB PHYs, 1 for OTG, 1 for standard USB, 1 for USB HSIC.
Add a compatible string for it, and describe the needed properties.
Signed-off-by: Chen-Yu Tsai
Tested-by: Maxime Ripard
---
Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 6 --
1 file changed, 4 insertions(
The Cubietruck-plus has a GL830 USB-to-SATA bridge connected to EHCI0,
and a USB3503 HSIC USB 2.0 hub connected to EHCI1. The USB3503's I2C
control interface is not connected.
This patch enables both EHCI controllers, adds a device node for the
USB hub, and includes sunxi-common-regulators.dtsi fo
Thanks for the infos!
I didn't know that someone is working on some patches for that board.
Philipp Rossak
On Aug 3, 2017 06:31, "Chen-Yu Tsai" wrote:
On Thu, Aug 3, 2017 at 7:25 AM, Philipp Rossak wrote:
> From: Philipp Rossak
>
> It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI
On 26 July 2017 at 21:45, Maxime Ripard
wrote:
> On Wed, Jul 26, 2017 at 10:09:41PM +0800, Chen-Yu Tsai wrote:
>> On Mon, Jul 24, 2017 at 9:58 PM, Chen-Yu Tsai wrote:
>> > Hi everyone,
>> >
>> > This is v3 of my MMC controller support series.
>> >
>>
>> [...]
>>
>> > Chen-Yu Tsai (10):
>> > clk
On Thu, Aug 3, 2017 at 7:19 PM, Ulf Hansson wrote:
> On 26 July 2017 at 21:45, Maxime Ripard
> wrote:
>> On Wed, Jul 26, 2017 at 10:09:41PM +0800, Chen-Yu Tsai wrote:
>>> On Mon, Jul 24, 2017 at 9:58 PM, Chen-Yu Tsai wrote:
>>> > Hi everyone,
>>> >
>>> > This is v3 of my MMC controller support s
On 3 August 2017 at 13:25, Chen-Yu Tsai wrote:
> On Thu, Aug 3, 2017 at 7:19 PM, Ulf Hansson wrote:
>> On 26 July 2017 at 21:45, Maxime Ripard
>> wrote:
>>> On Wed, Jul 26, 2017 at 10:09:41PM +0800, Chen-Yu Tsai wrote:
On Mon, Jul 24, 2017 at 9:58 PM, Chen-Yu Tsai wrote:
> Hi everyone
On Sun, Jul 23, 2017 at 06:27:40PM +0800, Icenowy Zheng wrote:
> From: Ondrej Jirman
>
> SY8106A is an I2C-controlled adjustable voltage regulator made by
> Silergy Corp.
>
> Add its device tree binding.
>
> Signed-off-by: Ondrej Jirman
> [Icenowy: Change commit message]
> Signed-off-by: Iceno
On Sun, Jul 23, 2017 at 10:13:50PM +0800, Icenowy Zheng wrote:
> Allwinner H3 features a thermal sensor like the one in A33, but has its
> register re-arranged, the clock divider moved to CCU (originally the
> clock divider is in ADC) and added a pair of bus clock and reset.
>
> Update the binding
On Mon, Jul 24, 2017 at 12:23:24AM +0100, Andre Przywara wrote:
> The ARM SMC mailbox binding describes a firmware interface to trigger
> actions in software layers running in the EL2 or EL3 exception levels.
> The term "ARM" here relates to the SMC instruction as part of the ARM
> instruction set,
On Thu, Jul 27, 2017 at 01:01:36PM +0800, Yong Deng wrote:
> Add binding documentation for Allwinner V3s CSI.
>
> Signed-off-by: Yong Deng
> ---
> .../devicetree/bindings/media/sun6i-csi.txt| 49
> ++
> 1 file changed, 49 insertions(+)
> create mode 100644 Documenta
On Thu, Aug 3, 2017 at 8:02 PM, Ulf Hansson wrote:
> On 3 August 2017 at 13:25, Chen-Yu Tsai wrote:
>> On Thu, Aug 3, 2017 at 7:19 PM, Ulf Hansson wrote:
>>> On 26 July 2017 at 21:45, Maxime Ripard
>>> wrote:
On Wed, Jul 26, 2017 at 10:09:41PM +0800, Chen-Yu Tsai wrote:
> On Mon, Jul 2
On Tue, Aug 1, 2017 at 10:54 PM, Icenowy Zheng wrote:
> The V3s pin controller doesn't have the bank 0 (starts at address
> 0x200), which is like A33. However, this is not workarounded when
was not worked around
"Work around" is a verb phrase. "Workarou
On Sun, Jul 30, 2017 at 2:35 PM, sufi al hussaini hassani kamili
raheemi wrote:
> Hi All,
>
> I am not able to get USB0 to work in host mode.
> This is an Olimex A20 Olinuxino micro and I have set `dr_mode = "host";` in
> the dts. I have compiled the kernel with USB support and the other USBs are
在 2017-08-04 10:23，Chen-Yu Tsai 写道：
On Tue, Aug 1, 2017 at 10:54 PM, Icenowy Zheng wrote:
The V3s pin controller doesn't have the bank 0 (starts at address
0x200), which is like A33. However, this is not workarounded when
was not worked around
"Work
On Tue, Aug 1, 2017 at 9:12 PM, Icenowy Zheng wrote:
> From: Icenowy Zheng
>
> Allwinner H3 has two special TCONs without channel 0.
>
> Add support for this kind of TCON.
>
> Signed-off-by: Icenowy Zheng
Ideally you would split this into two patches. The first one would add
the quirks support
On Wed, Jul 26, 2017 at 3:14 PM, Chen-Yu Tsai wrote:
> On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng wrote:
>> From: Chen-Yu Tsai
>>
>> This patch utilizes the new PLL clk notifier to gate then ungate the
>> PLL CPU clock after rate changes. This should prevent any system hangs
>> resulting fro
On Mon, Jul 24, 2017 at 11:10 AM, Chen-Yu Tsai wrote:
> On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng wrote:
>> The CPUX clock, which is the main clock of the ARM core on Allwinner H3,
>> can be adjusted by changing the frequency of the PLL_CPUX clock.
>>
>> Allowing setting parent clock for the
Hi,
On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng wrote:
> From: Jernej Skrabec
>
> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set.
>
> Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
>
> Signed-off-by: Jernej Skrabec
> Signed-off-by: Icenowy Zheng
> ---
> drivers/clk/
于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai 写到:
>Hi,
>
>On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng wrote:
>> From: Jernej Skrabec
>>
>> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be
>set.
>>
>> Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
>>
>> Signed-off-by: Jern
On Thu, Jul 20, 2017 at 6:29 PM, Jonathan Liu wrote:
> The physical size of the panel is 105.5 (W) x 67.2 (H) x 4.05 (D) mm
> but the active display area is 95.04 (W) x 53.856 (H) mm.
>
> The width and height should be set to the active display area.
>
> Signed-off-by: Jonathan Liu
You probably
On Fri, Aug 4, 2017 at 12:16 PM, Icenowy Zheng wrote:
>
>
> 于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai 写到:
>>Hi,
>>
>>On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng wrote:
>>> From: Jernej Skrabec
>>>
>>> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be
>>set.
>>>
>>> Add C
28 matches
Mail list logo
