[linux-sunxi] Re: [PATCH v2 06/10] arm64: allwinner: a64: Add devicetree binding for DMA controller

On Sat, Sep 23, 2017 at 6:34 PM, Stefan Bruens wrote: > On Mittwoch, 20. September 2017 22:53:00 CEST Rob Herring wrote: >> On Sun, Sep 17, 2017 at 05:19:52AM +0200, Stefan Brüns wrote: >> > The A64 is register compatible with the H3, but has a different number >> >

[linux-sunxi] [PATCH v3 10/10] arm64: allwinner: a64: add dma controller references to spi nodes

The spi controller nodes omit the dma controller/channel references, add it. This does not yet enable DMA for SPI transfers, as the spi-sun6i driver lacks support for DMA, but always uses PIO to the FIFO. Signed-off-by: Stefan Brüns --- Changes in v3: None Changes

[linux-sunxi] [PATCH v3 00/10] Commit 3a03ea763a67 ("dmaengine: sun6i: Add support for Allwinner A83T

(sun8i) variant") and commit f008db8c00c1 ("dmaengine: sun6i: Add support for Allwinner H3 (sun8i) variant") added support for the A83T resp. H3, but missed some differences between the original A31 and A83T/H3. The first patch adds a callback to the controller config to set the clock autogating

[linux-sunxi] [PATCH v3 05/10] dmaengine: sun6i: Move number of pchans/vchans/request to device struct

Preparatory patch: If the same compatible is used for different SoCs which have a common register layout, but different number of channels, the channel count can no longer be stored in the config. Store it in the device structure instead. Signed-off-by: Stefan Brüns

[linux-sunxi] [PATCH v3 03/10] dmaengine: sun6i: Restructure code to allow extension for new SoCs

The current code mixes three distinct operations when transforming the slave config to register settings: 1. special handling of DMA_SLAVE_BUSWIDTH_UNDEFINED, maxburst == 0 2. range checking 3. conversion of raw to register values As the range checks depend on the specific SoC, move these

[linux-sunxi] [PATCH v3 07/10] dmaengine: sun6i: Retrieve channel count/max request from devicetree

To avoid introduction of a new compatible for each small SoC/DMA controller variation, move the definition of the channel count to the devicetree. The number of vchans is no longer explicit, but limited by the highest port/DMA request number. The result is a slight overallocation for SoCs with a

[linux-sunxi] [PATCH v3 09/10] arm64: allwinner: a64: Add device node for DMA controller

The A64 SoC has a DMA controller that supports 8 DMA channels to and from various peripherals. The last used DRQ port is 27. Add a device node for it. Signed-off-by: Stefan Brüns --- Changes in v3: - Drop leading 0 from dma controller unit name Changes in v2:

[linux-sunxi] [PATCH v3 06/10] arm64: allwinner: a64: Add devicetree binding for DMA controller

The A64 is register compatible with the H3, but has a different number of dma channels and request ports. Attach additional properties to the node to allow future reuse of the compatible for controllers with different number of channels/requests. If dma-requests is not specified, the register

[linux-sunxi] [PATCH v3 04/10] dmaengine: sun6i: Enable additional burst lengths/widths on H3

The H3 supports bursts lengths of 1, 4, 8 and 16 transfers, each with a width of 1, 2, 4 or 8 bytes. The register value for the the width is log2-encoded, change the conversion function to provide the correct value for width == 8. Signed-off-by: Stefan Brüns

[linux-sunxi] [PATCH v3 01/10] dmaengine: sun6i: Correct setting of clock autogating register for A83T/H3

The H83T uses a compatible string different from the A23, but requires the same clock autogating register setting. The H3 also requires setting the clock autogating register, but has the register at a different offset. Add three suitable callbacks for the existing controller generations and set

[linux-sunxi] [PATCH v3 08/10] dmaengine: sun6i: Add support for Allwinner A64 and compatibles

The A64 SoC has the same dma engine as the H3 (sun8i), with a reduced amount of physical channels. To allow future reuse of the compatible, leave the channel count etc. in the config data blank and retrieve it from the devicetree. Signed-off-by: Stefan Brüns

[linux-sunxi] [PATCH v3 02/10] dmaengine: sun6i: Correct burst length field offsets for H3

For the H3, the burst lengths field offsets in the channel configuration register differs from earlier SoC generations. Using the A31 register macros actually configured the H3 controller do to bursts of length 1 always, which although working leads to higher bus utilisation. Signed-off-by:

[linux-sunxi] [linux] Question about ccu-sun8i-r.c a83t patch

Hey Chen-Yu, Currently I'm working on a patch series to enable the IR interface on the A83T. To get it running I need to configure the R_CIR_RX Clock Register of the A83T. In one of your patches [1] you submitted the related struct for it: a83t_ir_clk (in file: