On Thu, Nov 15, 2018 at 2:19 PM wrote:
>
> From: Marcus Cooper
>
> The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot,
> 2 USB ports( 1 * USB-2 Host, 1 USB OTG), a 10/100M ethernet port using the
> SoC's integrated PHY, Wifi via an sdio wifi chip, HDMI, an IR receiver, a
> dua
On Wed, Nov 21, 2018 at 03:58:18PM -0500, Stefan Monnier wrote:
> > When powering up an AXP209, the default value for LDO3 output is
> > enabled. This works fine. However if for whatever reason, LDO3 is
> > disabled, for example by OS during reboot and u-boot enables LDO3
> > again, the PMIC shut
Render like lima will attach a fence to the framebuffer
dma_buf, display like sun4i should wait it finish before
show the framebuffer. Otherwise tearing will be observed.
Signed-off-by: Qiang Yu
---
drivers/gpu/drm/sun4i/sun4i_layer.c| 2 ++
drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 2 ++
dri
Thanks, thought linux-sunxi is enough.
Regards,
Qiang
On Wed, Nov 21, 2018 at 11:45 PM Jernej Škrabec
wrote:
>
> Hi,
>
> Dne ponedeljek, 19. november 2018 ob 15:33:11 CET je Qiang Yu napisal(a):
> > Render like lima will attach a fence to the framebuffer
> > dma_buf, display like sun4i should wai
Allwinner ARMv5 F1C100s has similar sram controller to sun4i A10
Add compatible strings for it.
Signed-off-by: Mesih Kilinc
---
drivers/soc/sunxi/sunxi_sram.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
index b4b0f34
The suniv ARMv5 F1C100s chip has similar sram controller to sun4i A10.
Add compatible string for it.
Signed-off-by: Mesih Kilinc
---
Documentation/devicetree/bindings/sram/sunxi-sram.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/sram/sunxi-sram.txt
The new F-series SoCs (suniv) from Allwinner use an stripped version of
the interrupt controller in A10/A13
Add support for it in irq-sun4i driver.
Signed-off-by: Mesih Kilinc
---
drivers/irqchip/irq-sun4i.c | 104 +++-
1 file changed, 74 insertions(+), 3
Add compatiple string for Allwinner suniv F1C100s CCU.
Add clock and reset definitions.
Signed-off-by: Mesih Kilinc
---
.../devicetree/bindings/clock/sunxi-ccu.txt| 1 +
include/dt-bindings/clock/suniv-ccu-f1c100s.h | 69 ++
include/dt-bindings/reset/suniv-ccu-f
Add compatible string for Allwinner suniv timer which is similar to
sun4i timer.
Signed-off-by: Mesih Kilinc
---
Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/timer/allwin
The suniv F1C100s SoC (the chip in some new F-series products of
Allwinner)
has a CCU which seems to be a stripped version of the CCU in SoCs after
sun6i.
Add support for the CCU.
Signed-off-by: Mesih Kilinc
---
drivers/clk/sunxi-ng/Kconfig | 5 +
drivers/clk/sunxi-ng/Makefile
Lichee Pi Nano is a F1C100s board by Lichee Pi.
Add initial device tree for it.
Signed-off-by: Icenowy Zheng
Signed-off-by: Mesih Kilinc
---
arch/arm/boot/dts/Makefile| 2 ++
arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 26 +++
2 files change
Add compatible string for Allwinner suniv F1C100s SoC's pinctrl.
Signed-off-by: Mesih Kilinc
---
Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
b/Doc
This is the third version of RFC patchset for Allwinner ARMv5 F1C100s
SoC. Addressed comment from Maxime Ripard and fixed device tree
bindings to not include patterns. Also sram and watchdog compatibles
added for F1C100s.
irqchip code reworked to include a struct to differentiate chips.
Thanks!
Allwinner ARMv5 F1C100s has similar watchdog timer to sun6i A31.
Add compatible string for it.
Signed-off-by: Mesih Kilinc
---
drivers/watchdog/sunxi_wdt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
index c6c7365..bc70742 10064
The suniv (new F-series) chip has a timer with less functionality than
the A10 timer, e.g. it has only 3 channels.
Add a new compatible for it. As we didn't use the extra channels on A10
either now, the code needn't to be changed.
The suniv chip is based on ARM926EJ-S CPU, thus it has no architec
Add new Allwinner ARMv5 F1C100s SoC's compatible string
Signed-off-by: Mesih Kilinc
---
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt
b/Documentation/devicetree/bindings/arm/sunxi.txt
index e4b
The suniv F1C100s chip (several new F-series SoCs) of Allwinner has a
pin
controller like other SoCs from Allwinner.
Add support for it.
Signed-off-by: Mesih Kilinc
---
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile| 1 +
drivers/pinctrl/
Allwinner ARMv5 F1C100s has similar watchdog timer to sun6i A31.
Add definition for it.
Signed-off-by: Mesih Kilinc
---
Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
b/Documen
Allwinner also has some ARMv5 SoCs.
In order to add support for them, add a CONFIG_ARCH_SUNXI_V7 bool config
which is selected when a ARMv7 soc is selected, and make CONFIG_ARCH_SUNXI
a common option which is selected by both V7 and V5 sunxi option.
Signed-off-by: Mesih Kilinc
---
arch/arm/mach
F1C100s is one product with the suniv die, which has a 32MiB co-packaged
DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now,
add a
initial DTSI for it.
Signed-off-by: Mesih Kilinc
---
arch/arm/boot/dts/suniv-f1c100s.dtsi | 151 +++
1 file
Add compatible string for Alwinner suniv F1C100s SoC interrupt
controller which is stripped version of sun4i
Signed-off-by: Mesih Kilinc
---
.../devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
a/Documentation
Add option for Allwinner ARMv5 SoCs and SoC F1C100s (which has a die
used for many new F-series products, including F1C100A, F1C100s, F1C200s,
F1C500, F1C600).
Signed-off-by: Mesih Kilinc
---
arch/arm/mach-sunxi/Kconfig | 16 +++-
arch/arm/mach-sunxi/sunxi.c | 10 ++
2 files
> When powering up an AXP209, the default value for LDO3 output is
> enabled. This works fine. However if for whatever reason, LDO3 is
> disabled, for example by OS during reboot and u-boot enables LDO3
> again, the PMIC shuts down (without setting an interrupt) causing the
> board to hang. This
> + Increases the voltage by 1.6 mV per uS until the final voltage has
> + been reached. Note that the scaling is in 25 mV steps and thus
> + the slew rate in reality is about 25 mV/31.250 uS.
[...]
> + Increases the voltage by 0.8 mV per uS until the final voltage has
> + been
On Wed, Nov 21, 2018 at 08:05:24PM +0200, Priit Laes wrote:
> This is a resend/v2 of a "Stop AXP from crashing when enabling LDO3" series,
> posted by Olliver Schinagl in March 2017. Unfortunately it never got past
> initial discussion [1], but most Olimex Lime2 boards are still running
> into this
From: Olliver Schinagl
The AXP209 has a few 'magisc-ish' values that are better served with
clear defines.
Signed-off-by: Olliver Schinagl
Signed-off-by: Priit Laes
Acked-by: Maxime Ripard
---
drivers/power/axp209.c | 14 +++---
include/axp209.h | 13 +
2 files chan
From: Olliver Schinagl
The AXP209 LDO3 regulator supports voltage rate control, or can set a
slew rate.
This allows for the power to gradually rise up to the desired voltage,
instead of spiking up as fast as possible. Reason to have this can be
to reduce the inrush currents for example.
There a
From: Priit Laes
The lime2 features a too large capacitor on the LDO3 output, which
causes the PMIC to shutdown when enabling power. To be able to still
boot up however, we must gradually enable power on LDO3 for this board.
We do this by enabling both the inrush quirk and the maximum slope the
From: Olliver Schinagl
Currently during init, we enable all power, then enable the dram and
after that check whether there was an error during power-up.
This makes little sense, we should enable power and then check if power
was brought up properly before we continue to initialize other things.
From: Olliver Schinagl
When we clear a pmic_bus bit, we do a read-modify-write operation.
We waste some time however, by writing back the exact samea value
that was already set in the chip. Let us thus only do the write
in case data was changed.
Signed-off-by: Olliver Schinagl
Signed-off-by: Pr
From: Olliver Schinagl
Use the standard BIT() macro for bitfield definitions in headers.
Signed-off-by: Olliver Schinagl
Signed-off-by: Priit Laes
Acked-by: Maxime Ripard
---
include/axp209.h | 34 ++
1 file changed, 18 insertions(+), 16 deletions(-)
diff --g
From: Olliver Schinagl
Some boards feature a capacitance on LDO3's output that is too large,
causing inrush currents which as a result, shut down the AXP209. This
has been reported before, without knowing the actual cause.
A fix appeared to be done with
commit 0e6e34ac8dbb ("sunxi: Olimex A20 bo
From: Olliver Schinagl
The lime2 features a too large capacitor on the LDO3 output, which
causes the PMIC to shutdown when enabling power. To be able to still
boot up however, we must gradually enable power on LDO3 for this board.
We do this by enabling both the inrush quirk and the maximum slop
From: Olliver Schinagl
Use a define for the chip version mask on the axp209.
Signed-off-by: Olliver Schinagl
Signed-off-by: Priit Laes
Acked-by: Maxime Ripard
---
drivers/power/axp209.c | 5 +
include/axp209.h | 2 ++
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/d
This is a resend/v2 of a "Stop AXP from crashing when enabling LDO3" series,
posted by Olliver Schinagl in March 2017. Unfortunately it never got past
initial discussion [1], but most Olimex Lime2 boards are still running
into this bug.
When powering up an AXP209, the default value for LDO3 output
Hi,
Dne ponedeljek, 19. november 2018 ob 15:33:11 CET je Qiang Yu napisal(a):
> Render like lima will attach a fence to the framebuffer
> dma_buf, display like sun4i should wait it finish before
> show the framebuffer. Otherwise tearing will be observed.
Please resend this patch to all emails lis
Add Allwinner SoC T3 document and fix format.
Signed-off-by: Hao Zhang
---
Documentation/devicetree/bindings/arm/sunxi.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt
b/Documentation/devicetree/bindings/arm/sunxi.txt
inde
The T3/R40/V40 using the same sdk and config file in allwinner
sdk, it seem they are the same SOC just with different name, so
compatible with R40.
The t3-cqa3t-bv3 based on Allwinner T3 SoC, it has various connectors,
leds, buttons, and sell on:
https://item.taobao.com/item.htm?spm=2013.1.w4023-4
Initial Allwinner T3 support.
Allwinner T3 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU, and a
Mali400 MP2 GPU from ARM. It is a not-pin-compatible quad core sucessor
of the A20). It's also known as the Allwinner R40.
Hao Zhang (2):
ARM: dts: sun8i: Add board dts file for t3-cqa3t-bv3.
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