On Wed, Mar 27, 2019 at 8:18 AM megous via linux-sunxi
wrote:
>
> From: Ondrej Jirman
>
> Add pin definitions for UART2 PB pins. These are used on TBS-A711
> tablet.
>
> Signed-off-by: Ondrej Jirman
> ---
> arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
> 1 file changed, 5 insertions(+)
>
> diff
On Wed, Mar 27, 2019 at 8:49 AM megous via linux-sunxi
wrote:
>
> From: Ondrej Jirman
>
> This is inspired by the similar patch for H3. Original description
> applies, and is copied below:
>
> The cooling device properties, like "#cooling-cells" and
> "dynamic-power-coefficient", should either be
From: Ondrej Jirman
A83T DTSI has cpu clocks defined only on the first CPU in each cluster.
We can bring down any CPU in the cluster, so we need to define clock
for each CPU, so that the system knows what clock to use if the first
CPU is down.
Signed-off-by: Ondrej Jirman
---
arch/arm/boot/dts
From: Ondrej Jirman
This series adds some properties to prepare for passive cooling via
CPU frequency down-regulation, and fixes cpufreq for various CPU hotplug
situations.
#cooling-cells patch is not strictly necessary now, but now that SID
changes are soon to be merged, thermal sensor patches
From: Ondrej Jirman
Enable to use CPUs as cooling device in the future, by adding
"#cooling-cells" to each CPU node. This property should be present for
all the CPUs of a cluster. If these are present only for a subset of
CPUs of a cluster then things will start falling apart as soon as the
CPUs
On Tue, Mar 19, 2019 at 4:26 PM Maxime Ripard wrote:
>
> On Mon, Mar 11, 2019 at 08:28:22PM +0530, Jagan Teki wrote:
> > On Mon, Mar 11, 2019 at 7:39 PM Maxime Ripard
> > wrote:
> > >
> > > On Thu, Mar 07, 2019 at 09:24:02PM +0530, Jagan Teki wrote:
> > > > On Thu, Mar 7, 2019 at 9:09 PM Maxime
On Tue, 12 Mar 2019 23:22:43 +0800, Icenowy Zheng wrote:
> The pinctrl driver of V3s is already available and used in the kernel,
> but the compatible string of it is forgotten to be added.
>
> Add the missing compatible string.
>
> Signed-off-by: Icenowy Zheng
> ---
> .../devicetree/bindings/p
On Tue, 12 Mar 2019 23:22:45 +0800, Icenowy Zheng wrote:
> The Allwinner V3 SoC, despite come with the same die with V3s, has more
> GPIO pins than V3s, and a different compatible string for pinctrl is
> needed.
>
> Add the compatible string for V3 pinctrl.
>
> Signed-off-by: Icenowy Zheng
> ---
On Tue, 12 Mar 2019 23:22:48 +0800, Icenowy Zheng wrote:
> When adding the R40 compatible string to the binding document, a + is
> left behind the string, which seems to be a fault when dealing with
> patches.
>
> Remove the bogus + sign.
>
> Signed-off-by: Icenowy Zheng
> ---
> Documentation/d
On Tue, 12 Mar 2019 23:22:49 +0800, Icenowy Zheng wrote:
> Despite Allwinner V3 and V3s shares the same die, one peripheral (I2S)
> is only available on V3, and thus the clocks is not declared for V3s
> CCU.
>
> Add a V3 CCU compatible string to the binding to prepare for a CCU
> driver that provi
On Tue, Mar 12, 2019 at 11:22:50PM +0800, Icenowy Zheng wrote:
> Allwinner V3 has the same main die with V3s, but with more pins wired.
> There's a I2S bus on V3 that is not available on V3s.
>
> Add the V3-only peripheral's clocks and reset to the V3s CCU driver,
> bound to a new V3 compatible st
On Tue, 12 Mar 2019 23:22:51 +0800, Icenowy Zheng wrote:
> Shenzhen SoChip Technology Co., Ltd. is a hardware vendor that produces
> EVBs with Allwinner chips. There's also a SoC named S3 that is developed
> by Allwinner (based on Allwinner V3/V3s) but branded SoChip.
>
> Add the vendor prefix for
On Tue, 12 Mar 2019 23:22:52 +0800, Icenowy Zheng wrote:
> Allwinner V3/V3s/S3L and SoChip S3 SoCs share the same die, but with
> different package (V3 is BGA, without co-packaged DRAM, V3s is QFP,
> with co-packaged DDR2, S3 is BGA, with co-packaged DDR3, S3L is BGA
> pin-compatible with S3, but w
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