于 2020年10月27日 GMT+08:00 上午2:32:30, Maxime Ripard 写到:
>On Mon, Oct 26, 2020 at 10:21:00PM +0800, Icenowy Zheng wrote:
>> PineCube is an IP camera development kit released by Pine64.
>>
>> It comes with the following compoents:
>>
>> - A mainboard with Sochip S3 SoC, a 16MByte SPI Flash,
From: Marcus Cooper
Add the I2S2 node connected to the HDMI interface.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Acked-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 14 ++
1 file changed, 14 insertions(+)
From: Marcus Cooper
Extend the functionality of the driver to include support of 20 and
24 bits per sample.
Signed-off-by: Marcus Cooper
Acked-by: Maxime Ripard
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 11 +--
1 file changed, 9
We are actually using a complex formula to just return a bunch of
simple values. Also this formula is wrong for sun4i when calling
get_wss() the function return 4 instead of 3.
Replace this with a simpler switch case.
Also drop the i2s params which is unused and return a simple int as
returning
As slots and slot_width can be set manually using set_tdm().
These values are then kept in sun4i_i2s struct.
So we need to check if these values are set or not.
This is not done actually and will trigger a bug.
For example, if we set to the simple soundcard in the device-tree
dai-tdm-slot-width =
Checkpatch script produces warning:
WARNING: function definition argument 'const struct sun4i_i2s *'
should also have an identifier name.
Let's fix this by adding identifier name to get_bclk_parent_rate()
and set_fmt() callback definition.
Acked-by: Maxime Ripard
Signed-off-by: Clément Péron
Like A83T the Allwinner H3 doesn't have the DMA reception available for
some audio interfaces.
As it's already documented for A83T convert this to an enum and add the H3
interface.
Acked-by: Rob Herring
Signed-off-by: Clément Péron
---
Enable Allwinner I2S driver for arm64 defconfig.
Signed-off-by: Clément Péron
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 17a2df6a263e..3f89f427a355 100644
---
From: Jernej Skrabec
H6 I2S is very similar to H3, except that it supports up to 16 channels
and thus few registers have fields on different position.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Acked-by: Maxime Ripard
Acked-by: Rob Herring
Acked-by: Chen-Yu Tsai
From: Jernej Skrabec
H6 I2S is very similar to that in H3, except it supports up to 16
channels.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
sound/soc/sunxi/sun4i-i2s.c | 222
1
From: Marcus Cooper
On the newer SoCs such as the H3 and A64 this is set by default
to transfer a 0 after each sample in each slot. However the A10
and A20 SoCs that this driver was developed on had a default
setting where it padded the audio gain with zeros.
This isn't a problem while we have
Hi,
This is the same as v7 but rebased on next-20201026 and added a comment
about slots and slot_width.
A proper sound card will be introduced later.
This was tested on H6 only.
Regards,
Clement
Change since v7:
- rebase on next-20201026
- comment about slots and slot_width
Change since v6
From: Jernej Skrabec
Add Allwinner H6 I2S1 node connected to HDMI interface.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Acked-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 +
1 file changed, 13 insertions(+)
The FIFO TX reg is volatile and sun8i i2s register
mapping is different from sun4i.
Even if in this case it's doesn't create an issue,
Avoid setting some regs that are undefined in sun8i.
Acked-by: Maxime Ripard
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
From: Marcus Cooper
Add H3/H5 I2S2 node connected to the HDMI interface.
Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Cooper
Acked-by: Chen-Yu Tsai
Signed-off-by: Clément Péron
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git
From: Samuel Holland
Because SUN4I_I2S_FIFO_CTRL_REG is volatile, writes done while the
regmap is cache-only are ignored. To work around this, move the
configuration to a callback that runs while the ASoC core has a
runtime PM reference to the device.
Signed-off-by: Samuel Holland
Reviewed-by:
On Mon, Oct 26, 2020 at 10:21:00PM +0800, Icenowy Zheng wrote:
> PineCube is an IP camera development kit released by Pine64.
>
> It comes with the following compoents:
>
> - A mainboard with Sochip S3 SoC, a 16MByte SPI Flash, AXP209 PMIC,
> a power-only microUSB connector, a USB Type-A
On Fri, Oct 23, 2020 at 07:45:32PM +0200, Paul Kocialkowski wrote:
> This series introduces support for MIPI CSI-2, with the A31 controller that is
> found on most SoCs (A31, V3s and probably V5) as well as the A83T-specific
> controller. While the former uses the same MIPI D-PHY that is already
On Fri, Oct 23, 2020 at 07:45:44PM +0200, Paul Kocialkowski wrote:
> The A83T supports MIPI CSI-2 with a composite controller, covering both the
> protocol logic and the D-PHY implementation. This controller seems to be found
> on the A83T only and probably was abandonned since.
>
> This
On Fri, Oct 23, 2020 at 07:45:46PM +0200, Paul Kocialkowski wrote:
> The A83T MIPI CSI-2 apparently produces interrupts regardless of the mask
> registers, for example when a transmission error occurs.
>
> This generates quite a flood when unsolicited interrupts are received on
> each received
On Fri, Oct 23, 2020 at 07:45:43PM +0200, Paul Kocialkowski wrote:
> This introduces YAML bindings documentation for the A83T MIPI CSI-2
> controller.
>
> Signed-off-by: Paul Kocialkowski
What is the difference with the a31/v3s one?
> ---
> .../media/allwinner,sun8i-a83t-mipi-csi2.yaml | 158
On Fri, Oct 23, 2020 at 07:45:42PM +0200, Paul Kocialkowski wrote:
> MIPI CSI-2 is supported on the V3s with an A31 controller, which seems
> to be used on all Allwinner chips supporting it, except for the A83T.
> The controller is connected to CSI0 through fwnode endpoints.
> The mipi_csi2_in
On Fri, Oct 23, 2020 at 07:45:37PM +0200, Paul Kocialkowski wrote:
> Bits related to the interface data width do not have any effect when
> the CSI controller is taking input from the MIPI CSI-2 controller.
I guess it would be clearer to mention that the data width is only
applicable for parallel
On Fri, Oct 23, 2020 at 07:45:35PM +0200, Paul Kocialkowski wrote:
> This allows selecting a dedicated CMA memory pool (specified via
> device-tree) instead of the default one.
>
> Signed-off-by: Paul Kocialkowski
Why would that be needed?
> ---
>
On Fri, Oct 23, 2020 at 07:45:34PM +0200, Paul Kocialkowski wrote:
> The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
> is already supported and used for MIPI DSI this adds support for the
> former, to be used with MIPI CSI-2.
>
> This implementation is inspired by the
PineCube is an IP camera development kit released by Pine64.
It comes with the following compoents:
- A mainboard with Sochip S3 SoC, a 16MByte SPI Flash, AXP209 PMIC,
a power-only microUSB connector, a USB Type-A connector, a 10/100Mbps
Ethernet port and FPC connectors for camera and daughter
The reference design of Allwinner V3 series uses an
AXP203 or AXP209 PMIC attached to the I2C0 bus of the SoC, although the
first community-available V3s board, Lichee Pi Zero, omitted it.
Allow to introduce support for the PMIC on boards with it.
Signed-off-by: Icenowy Zheng
---
This commit imports device tree files that are related to Allwinner V3
series from Linux commit 3650b228f83a ("Linux 5.10-rc1").
Signed-off-by: Icenowy Zheng
---
arch/arm/dts/sun8i-s3-lichee-zero-plus.dts| 53 +++
arch/arm/dts/sun8i-s3-pinecube.dts| 235 +
A new compatible string is introduced for V3 CCU, because it has a few
extra features available.
Add the compatible string to the clock driver. As the extra features are
not touched, just share the description struct now.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi/clk_v3s.c | 2 ++
1
A new compatible string is introduced for V3 GPIO, because it has more
pins available than V3s.
Add the compatible string to the GPIO driver.
Signed-off-by: Icenowy Zheng
---
drivers/gpio/sunxi_gpio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/sunxi_gpio.c
Allwinner V3/Sochip S3 uses the same die with Allwinner V3s/S3L, but V3 comes
with no co-packaged DDR (DDR3 is usually used externally), and S3L comes
with co-packaged DDR3.
Add support for Allwinner V3/S3 chips by add SoC names to original V3s
choice, and allow to select DDR3.
Signed-off-by:
This patchset tries to add support for Allwinner V3/S3 and Pine64
PineCube to U-Boot.
First 3 patches adds support for Allwinner V3/S3 to U-Boot by expanding
the code of V3s and add compatible strings to individual drivers.
Then a patch allows V3 series chips to utilize the AXP20x driver in
> By referring to linux/phy.h, NA means not applicable. This surely
> do not apply when RGMII is really in use.
It means the PHY driver should not touch the mode, something else has
set it up. That could be strapping, the bootloader, ACPI firmware,
whatever.
> I think no document declares RGMII
On Sun, Oct 25, 2020 at 12:25:15AM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai
>
> The Ethernet PHY on the Bananapi M64 has the RX and TX delays
> enabled on the PHY, using pull-ups on the RXDLY and TXDLY pins.
>
> Fix the phy-mode description to correct reflect this so that the
>
On Fri, Oct 23, 2020 at 08:48:58PM +0200, Jernej Skrabec wrote:
> RX and TX delay are provided by ethernet PHY. Reflect that in ethernet
> node.
>
> Fixes: 44a94c7ef989 ("arm64: dts: allwinner: H5: Restore EMAC changes")
> Signed-off-by: Jernej Skrabec
Applied, thanks
Maxime
--
You received
On Fri, Oct 23, 2020 at 09:49:02PM +0200, Jernej Skrabec wrote:
> Ethernet PHY provides RX and TX delay on both models, A and B. Although
> schematic for model A suggests only TX delay, network never worked with
> such configuration.
>
> Fix ethernet node to reflect PHY delays.
>
> Fixes:
On Fri, Oct 23, 2020 at 07:45:44PM +0200, Paul Kocialkowski wrote:
> +static int sun8i_a83t_mipi_csi2_v4l2_setup(struct sun8i_a83t_mipi_csi2_dev
> *cdev)
> +{
> + struct sun8i_a83t_mipi_csi2_video *video = >video;
> + struct v4l2_subdev *subdev = >subdev;
> + struct
On Fri, Oct 23, 2020 at 07:45:40PM +0200, Paul Kocialkowski wrote:
> +static int sun6i_mipi_csi2_s_stream(struct v4l2_subdev *subdev, int on)
> +{
> + struct sun6i_mipi_csi2_video *video =
> + sun6i_mipi_csi2_subdev_video(subdev);
> + struct sun6i_mipi_csi2_dev *cdev =
于 2020年10月26日 GMT+08:00 上午1:28:48, Andrew Lunn 写到:
>> >> 1. As the PHY chip has hardware configuration for configuring
>delays,
>> >> we should at least have a mode that respects what's set on the
>> >hardware.
>> >
>> >Yes, that is PHY_INTERFACE_MODE_NA. In DT, set the phy-mode to "".
>Or
>>
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