On Sat, Dec 12, 2020 at 3:33 AM Sergio Sota wrote:
>
> Hi Clement,
>
> yes, tve0 is only for VGA/CVBS video output (which we don't use right now)
> But just in case we have enabled this controller and the result is the same.
>
> You're probably right about the I2C port (as the binding suggest)
Hi *Clement*,
yes, *tve0* is only for *VGA/CVBS* video output (which we don't use right
now)
But just in case *we have enabled this controller and the result is the
same*.
You're probably right about the *I2C* port (as the binding suggest) The
thing is
we are using the *olimex olinuxino tft
Hi Sergio,
Sorry looks like the tve0 is only required for composite / VGA output.
Which LCD Panel do you use ?
Looks like the bindings you are using should be declared on a I2C bus.
Hi Sergio,
Maybe you missed enabling tve0 ?
https://elixir.bootlin.com/linux/v5.9.13/source/arch/arm/boot/dts/sun5i.dtsi#L244
Also could you send the bootlog is this doesn't fix your issue.
Clement
On Fri, 11 Dec 2020 at 17:13, Sergio Sota wrote:
>
> Hi Clement,
>
> this week we have had no
Hi* Clement,*
this week we have had no luck with *Allwinner A13* *video decoding*, here
you
can find my *device tree*. We have added *panel description* (before we used
an uboot configuration) *front-end*, *back-end* and *tcon*. Also on linux
mainline
kernel (5.9.11) we have selected
Add myself as maintainer of the A83T MIPI CSI-2 bridge media driver.
Signed-off-by: Paul Kocialkowski
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index a1352171778b..3b48612657b6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -717,6
MIPI CSI-2 is supported on the A83T with a dedicated controller that
covers both the protocol and D-PHY. It can be connected to the CSI
interface as a V4L2 subdev through the fwnode graph.
This is not done by default since connecting the bridge without a
subdev attached to it will cause a failure
The A83T supports MIPI CSI-2 with a composite controller, covering
both the protocol logic and the D-PHY implementation. This controller
seems to be found on the A83T only and probably was abandoned since.
This implementation splits the protocol and D-PHY registers and
uses the PHY framework
This introduces YAML bindings documentation for the A83T MIPI CSI-2
controller.
Signed-off-by: Paul Kocialkowski
Reviewed-by: Rob Herring
---
.../media/allwinner,sun8i-a83t-mipi-csi2.yaml | 147 ++
1 file changed, 147 insertions(+)
create mode 100644
Add myself as maintainer of the A31 MIPI CSI-2 bridge media driver.
Signed-off-by: Paul Kocialkowski
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0644128640fb..a1352171778b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -709,6
MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge
controller. The controller uses a separate D-PHY, which is the same
that is otherwise used for MIPI DSI, but used in Rx mode.
On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does
not have access to any
The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 bridge
found on Allwinner SoCs such as the A31 and V3/V3s.
It is a standalone block, connected to the CSI controller on one side
and to the MIPI D-PHY block on the other. It has a dedicated address
space, interrupt line and clock.
It is
This introduces YAML bindings documentation for the A31 MIPI CSI-2
controller.
Signed-off-by: Paul Kocialkowski
---
.../media/allwinner,sun6i-a31-mipi-csi2.yaml | 149 ++
1 file changed, 149 insertions(+)
create mode 100644
The A31 CSI controller supports a MIPI CSI-2 bridge input, which has
its own dedicated port in the fwnode graph.
Support for this input is added with this change:
- two pads are defined for the media entity instead of one
and only one needs to be connected at a time;
- the pads currently match
The A31 CSI controller supports two distinct input interfaces:
parallel and an external MIPI CSI-2 bridge. The parallel interface
is often connected to a set of hardware pins while the MIPI CSI-2
bridge is an internal FIFO-ish link. As a result, these two inputs
are distinguished as two different
Bits related to the interface data width are only applicable to the
parallel interface and are irrelevant when the CSI controller is taking
input from the MIPI CSI-2 controller.
In prevision of adding support for this case, set these bits
conditionally so there is no ambiguity. The conditional
V4L2 has a common helper which can be used for calculating the number
of stored bits per pixels of a given (stored) image format.
Use the helper-returned structure instead of our own switch/case list.
Note that a few formats are not in that list so we keep them as
special cases.
The custom
The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
is already supported and used for MIPI DSI this adds support for the
former, to be used with MIPI CSI-2.
This implementation is inspired by Allwinner's V3s Linux SDK
implementation, which was used as a documentation base.
As some D-PHY controllers support both Rx and Tx mode, we need a way for
users to explicitly request one or the other. For instance, Rx mode can
be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI.
Introduce new MIPI D-PHY PHY submodes to use with PHY_MODE_MIPI_DPHY.
The default
Besides giving pointers to the relevant functions for PHY mode and
submode configuration, this clarifies the need to set them before
powering on the PHY.
Signed-off-by: Paul Kocialkowski
Reviewed-by: Maxime Ripard
---
Documentation/driver-api/phy/phy.rst | 18 ++
1 file
This series introduces support for MIPI CSI-2, with the A31 controller that is
found on most SoCs (A31, V3s and probably V5) as well as the A83T-specific
controller. While the former uses the same MIPI D-PHY that is already supported
for DSI, the latter embeds its own D-PHY.
In order to
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