On Mon, Mar 3, 2014 at 2:56 AM, Mark Brown broo...@kernel.org wrote:
On Sat, Mar 01, 2014 at 05:45:51PM +0100, Carlo Caione wrote:
index d59c826..0cef101 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -69,3 +69,4 @@ CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
On Mon, Mar 3, 2014 at 12:02 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Thu, Feb 27, 2014 at 08:34:22PM +0100, Carlo Caione wrote:
Added documentation for NMI irqchip.
Signed-off-by: Carlo Caione ca...@caione.org
---
.../allwinner,sun67i-sc-nmi.txt
Key)
- Regulators
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/configs/sunxi_defconfig | 1 +
drivers/mfd/Kconfig | 12 ++
drivers/mfd/Makefile | 1 +
drivers/mfd/axp20x.c | 250 +++
include/linux/mfd
Add ABI entries for the PEK found on PMU X-Powers AXP202 and AXP209.
Signed-off-by: Carlo Caione ca...@caione.org
---
Documentation/ABI/testing/sysfs-driver-input-axp-pek | 11 +++
1 file changed, 11 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-driver-input-axp-pek
AXP202 and AXP209 come with two synchronous step-down DC-DCs and five
LDOs. This patch introduces basic support for those regulators.
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/configs/sunxi_defconfig | 1 +
drivers/regulator/Kconfig| 7 +
drivers/regulator
This patch enables basic support for regulators found in AXP209 on
Cubieboard2.
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 44 +
1 file changed, 44 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2
as 4 configurable GPIOs.
This set of patches introduces the core driver and support for two different
subsystems:
- Regulators
- PEK (Power Enable Key)
Support for AXP209 in Cubieboard2 is also added.
Carlo Caione (7):
mfd: AXP20x: Add mfd driver for AXP20x PMIC
mfd: AXP20x
callback as in the v3 version of the NMI controller
driver (so no flag needed)
2) No poweroff functionality ? That would be really great to have.
Actually in [PATCH 1/7] I support the poweroff using the pm_power_off hook.
Best,
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Carlo Caione
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. The code is correct.
Where is writel (the used one) declared?
http://lxr.missinglinkelectronics.com/linux/arch/arm/include/asm/io.h#L307
Cheers,
Danny
Best,
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On Sat, Mar 1, 2014 at 11:40 PM, Carlo Caione ca...@caione.org wrote:
Therefore, (1 SW_INT_IRQNO_ENMI) will expand to (1 32) which is
useless on a 32 bit ARM, 1 being a 32 bit int.
Even on other 32 bit platforms, best you could hope for is (1 32) == 0,
not that useful.
It is really
This patch adds DTS entries for NMI controller as child of GIC.
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 9 +
arch/arm/boot/dts/sun7i-a20.dtsi | 9 +
2 files changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch
Allwinner A20/A31 SoCs have special registers to control / (un)mask /
acknowledge NMI. This NMI controller is separated and independent from GIC.
This patch adds a new irqchip to manage NMI.
Signed-off-by: Carlo Caione ca...@caione.org
---
drivers/irqchip/Makefile| 1 +
drivers/irqchip
trigger type in DTS
- new explanations in binding documentation
- added support for A31 (sun6i)
Changes since v3:
- changed compatibles
Carlo Caione (3):
ARM: sun7i/sun6i: irqchip: Add irqchip driver for NMI controller
ARM: sun7i/sun6i: dts: Add NMI irqchip support
ARM
, try harder to stay in topic.
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.
Right.
Right. So why are you doing them both?
Right == I'll fix it :)
Thank you,
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On Mon, Feb 10, 2014 at 9:08 PM, Lee Jones lee.jo...@linaro.org wrote:
On Sat, 08 Feb 2014, Carlo Caione wrote:
This patch adds a new dtsi for supporting axp20x.
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/boot/dts/axp20x.dtsi | 9 +
1 file changed, 9 insertions
On Mon, Feb 10, 2014 at 8:59 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi Carlo,
On Sat, Feb 08, 2014 at 05:03:47PM +0100, Carlo Caione wrote:
This patch adds a new dtsi for supporting axp20x.
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/boot/dts/axp20x.dtsi
them in the
DT too. Why do you need to declare the resources in both locations?
It's not really a need, I thought it was a bit clearer also to have
them in DT.
But I agree it is redundant. I'll fix in v2.
Thank you,
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On Mon, Feb 10, 2014 at 9:12 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi Carlo,
On Sat, Feb 08, 2014 at 05:03:48PM +0100, Carlo Caione wrote:
Bindings documentation for the axp20x driver. In this file also two
sub-nodes (PEK and regulators) are documented.
Signed-off
-by: Carlo Caione ca...@caione.org
---
drivers/mfd/Kconfig| 12 +++
drivers/mfd/Makefile | 1 +
drivers/mfd/axp20x.c | 251
+
include/linux/mfd/axp20x.h | 178
4 files changed, 442 insertions
On Mon, Feb 10, 2014 at 11:01 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Mon, Feb 10, 2014 at 09:37:37PM +0100, Carlo Caione wrote:
+Sub-nodes
+* regulators : Contain the regulator nodes. The regulators are bound
using
+their name as listed here: dcdc2
On Mon, Feb 10, 2014 at 11:34 PM, Carlo Caione ca...@caione.org wrote:
+static struct axp20x_dev *axp20x_pm_power_off;
This looks pretty unconventional. What's the point of it?
On a single board we can have multiple AXPs so I track which one is in
charge of powering off the board
Bindings documentation for the axp20x driver. In this file also two
sub-nodes (PEK and regulators) are documented.
Signed-off-by: Carlo Caione ca...@caione.org
---
Documentation/devicetree/bindings/mfd/axp20x.txt | 87
1 file changed, 87 insertions(+)
create mode 100644
This set of patches add prelinary support for PMIC X-Powers axp202 and axp209.
Only two subsystem are supported at the moment: power enable key (PEK) and
regulators. Drivers for these two sub-system will be submitted in later
patch-sets.
Carlo Caione (3):
mfd: axp20x: Add mfd driver for axp20x
This patch introduces the preliminary support for PMICs X-Powers AXP202
and AXP209. The core contains support only for two sub-modules (PEK
and regulators) that will be added with two different patch-sets.
Signed-off-by: Carlo Caione ca...@caione.org
---
drivers/mfd/Kconfig| 12
?
unmask_and_ack() plus IRQCHIP_ACK_ON_UNMASK are not really telling
what the heck is going on. You can restrict it to level irqs in the
core, but please use the proper functions and not some opencoded
hackery.
I'll do in case of v2.
Thanks,
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unmask_threaded_irq() function.
Unfortunately I cannot be sure whether the problem is still present
for the non threaded case since in the hardware I have the NMI
controller is only connected to the PMIC.
Considering that I have no way of checking what do you suggest?
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Carlo Caione
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You received
Several irqchip drivers require the level-triggered interrupt to be
acked before unmasking to avoid that a second interrupt is immediately
triggered. This small patch introduces a new irqchip flags that is used
to ack the IRQ line before it is unmasked.
Signed-off-by: Carlo Caione ca
On Thu, Feb 6, 2014 at 10:14 PM, Thomas Gleixner t...@linutronix.de wrote:
On Thu, 6 Feb 2014, Carlo Caione wrote:
Several irqchip drivers require the level-triggered interrupt to be
acked before unmasking to avoid that a second interrupt is immediately
triggered. This small patch introduces
the line
before unmasking it again.
Best,
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function has been
executed (calling the unmask callback)
Thank you for explaining this mess you couldn't be clearer than that.
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the
hard handler and the thread, so there's no way you can get an
interrupt flood during that time.
agree.
BTW fortunately we can talk about this also during FOSDEM ;)
Thank you,
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On Thu, Jan 16, 2014 at 1:39 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi Carlo,
On Sat, Jan 11, 2014 at 04:19:06PM +0100, Carlo Caione wrote:
Allwinner A20/A31 SoCs have special registers to control / (un)mask /
acknowledge NMI. This NMI controller is separated
want, although I think we'll
probably
head out for dinner and then to the Beerfest at 20pm at the latest.
I'll be in bruxelles around 4pm, a bit late :(
Anyway let me know if there will be people there.
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Allwinner A20/A31 SoCs have special registers to control / (un)mask /
acknowledge NMI. This NMI controller is separated and independent from GIC.
This patch adds a new irqchip to manage NMI.
Signed-off-by: Carlo Caione carlo.cai...@gmail.com
---
drivers/irqchip/Makefile| 1 +
drivers
This patch adds DTS entries for NMI controller as child of GIC.
Signed-off-by: Carlo Caione carlo.cai...@gmail.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 9 +
arch/arm/boot/dts/sun7i-a20.dtsi | 9 +
2 files changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi
Added documentation for NMI irqchip.
Signed-off-by: Carlo Caione carlo.cai...@gmail.com
---
.../allwinner,sun67i-sc-nmi.txt| 26 ++
1 file changed, 26 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/allwinner
On Wed, Jan 8, 2014 at 2:09 PM, Arnd Bergmann a...@arndb.de wrote:
On Wednesday 08 January 2014 12:49:10 Carlo Caione wrote:
+sc-nmi-intc@01c00030 {
+ compatible = allwinner,sun7i-sc-nmi;
+ interrupt-controller;
+ #interrupt-cells = 2;
+ reg = 0x01c00030 0x0c
On Wed, Jan 8, 2014 at 2:03 PM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 01/08/2014 12:49 PM, Carlo Caione wrote:
On Wed, Jan 8, 2014 at 12:29 PM, Arnd Bergmann a...@arndb.de wrote:
On Monday 06 January 2014, Carlo Caione wrote:
+Allwinner Sunxi NMI Controller
This patch adds DTS entry for NMI controller as child of GIC.
Signed-off-by: Carlo Caione carlo.cai...@gmail.com
---
arch/arm/boot/dts/sun7i-a20.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 4c25f81
Allwinner A20 SoCs have a special interrupt controller for managing NMI.
Three register are present to (un)mask, control and acknowledge NMI.
These two patches add a new irqchip driver in cascade with GIC.
Carlo Caione (2):
ARM: sun7i: Add irqchip driver for NMI controller
ARM: sun7i: dts
Allwinner A20 SoCs have special registers to control / (un)mask /
acknowledge NMI. This NMI controller is separated and independent from GIC.
This patch adds a new irqchip to manage NMI.
Signed-off-by: Carlo Caione carlo.cai...@gmail.com
---
drivers/irqchip/Makefile| 1 +
drivers
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