ice tree
>
> Ondrej Jirman (1):
> input: sun4i-lradc-keys - Add wakup support
>
> Samuel Holland (2):
> dt-bindings: sun4i-a10-lradc-keys: Accept wakeup-source property
> arm64: dts: allwinner: pinephone: Support volume key wakeup
Thanks, the entire series looks good t
PEK IRQs are
nested off of regmap-irq's threaded interrupt handler. The device core
ignores such interrupts, so to actually disable wakeup, we must
explicitly disable all non-wakeup interrupts during suspend.
Signed-off-by: Samuel Holland
Patch looks good to me:
Reviewed-by: Hans de
Hi,
On 13-01-2020 22:26, Dmitry Torokhov wrote:
Hi Samuel,
On Sun, Jan 12, 2020 at 09:20:32PM -0600, Samuel Holland wrote:
There are many devices, including several mobile battery-powered
devices, using other AXP variants as their PMIC. Enable them to use
the power key as a wakeup source.
Ar
On 13-01-2020 11:41, Hans de Goede wrote:
Hi,
On 13-01-2020 04:20, Samuel Holland wrote:
This driver attempts to avoid reporting wakeup events to userspace by
clearing a possible pending IRQ before IRQs are enabled during resume.
The assumption seems to be that userspace cannot cope with a
Hi,
On 13-01-2020 04:20, Samuel Holland wrote:
There are many devices, including several mobile battery-powered
devices, using other AXP variants as their PMIC. Enable them to use
the power key as a wakeup source.
Signed-off-by: Samuel Holland
Patch looks good to me:
Reviewed-by: Hans de
int axp20x_pek_probe(struct platform_device *pdev)
return 0;
}
+#if CONFIG_PM_SLEEP
As the kbuild test robot pointed out, you need to use #ifdef here.
Otherwise this patch looks good to me:
Reviewed-by: Hans de Goede
Regards,
Hans
+static int axp20x_pek_suspend(struct device *d
Hi,
On 13-01-2020 04:20, Samuel Holland wrote:
This driver attempts to avoid reporting wakeup events to userspace by
clearing a possible pending IRQ before IRQs are enabled during resume.
The assumption seems to be that userspace cannot cope with a KEY_POWER
press during resume. However, no othe
Hi,
On 13-05-19 12:34, U.Mutlu wrote:
Hans de Goede wrote on 05/13/2019 09:44 AM:
On 12-05-19 22:59, Uenal Mutlu wrote:
Increasing the SATA/AHCI DMA TX/RX FIFOs (P0DMACR.TXTS and .RXTS, ie.
TX_TRANSACTION_SIZE and RX_TRANSACTION_SIZE) from default 0x0 each
to 0x3 each, gives a write
Hi,
On 12-05-19 22:59, Uenal Mutlu wrote:
Increasing the SATA/AHCI DMA TX/RX FIFOs (P0DMACR.TXTS and .RXTS, ie.
TX_TRANSACTION_SIZE and RX_TRANSACTION_SIZE) from default 0x0 each
to 0x3 each, gives a write performance boost of 120 MiB/s to 132 MiB/s
from lame 36 MiB/s to 45 MiB/s previously.
Rea
Hi,
On 25-03-19 03:45, Chen-Yu Tsai wrote:
On Thu, Mar 21, 2019 at 5:30 PM Maxime Ripard wrote:
Hi,
The rest of the series is
Acked-by: Maxime Ripard
On Thu, Mar 21, 2019 at 04:48:44PM +0800, Chen-Yu Tsai wrote:
From: Chen-Yu Tsai
The AXP PMICs allow the user to disable current limiting
ressources added
by this serie, so no regression should come with it.
Patchs 1-7 should go via the ata tree
Patchs 8,9 should go via the sunxi tree
Acked-by: Maxime Ripard
The entire series looks good to me too:
Reviewed-by: Hans de Goede
Regards,
Hans
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You received this message because you
HI,
On 30-08-18 21:01, Corentin Labbe wrote:
Since PHY code is now handled by sun4i-a10-sata-phy, the code in
ahci_sunxi is useless, remove it.
Signed-off-by: Corentin Labbe
---
drivers/ata/ahci_sunxi.c | 93
1 file changed, 93 deletions(-)
with it.
The last patch(ata: ahci_sunxi: remove PHY code) should not be merged,
but will be resent for inclustion when all patchs will have hit linus
tree.
Thank you for your work on this, the entire series looks good to me:
Reviewed-by: Hans de Goede
Note I've one remark for the final d
chip.
Cc: sta...@vger.kernel.org
Signed-off-by: Icenowy Zheng
A quick internet search shows various problems with this device even under
Windows, so yes this seems like a good idea:
Acked-by: Hans de Goede
The NS1066 chip from the same vendor seems to also suffer from this
problem (its USB ID
Hi,
On 28-02-17 16:27, Icenowy Zheng wrote:
On newer Allwinner SoCs (H3 and after), the PHY0 node is routed to both
MUSB controller for peripheral and host support (the host support is
slightly broken), and a pair of EHCI/OHCI controllers, which provide a
better support for host mode.
Add suppo
HI,
On 22-01-17 10:39, Icenowy Zheng wrote:
20.01.2017, 16:04, "Hans de Goede" :
HI,
On 19-01-17 21:27, Karsten Merker wrote:
On Thu, Jan 19, 2017 at 11:10:08PM +0800, Icenowy Zheng wrote:
19.01.2017, 22:34, "Maxime Ripard" :
On Wed, Jan 18, 2017 at 04:09:32AM
iments with the MUSB in the A31s in host
mode I can report that I hadn't been able to get multiple HIDs
(in my case keyboard and mouse) working at the same time. The
keyboard alone worked without problems, the mouse alone worked
without problems, but when both were connected, only one of them
wo
Hi,
On 22-12-16 11:31, Chen-Yu Tsai wrote:
On Tue, Dec 20, 2016 at 12:17 AM, Hans de Goede wrote:
Hi,
On 19-12-16 17:06, Icenowy Zheng wrote:
19.12.2016, 23:30, "Hans de Goede" :
Hi,
On 19-12-16 16:22, Icenowy Zheng wrote:
Hi everyone,
Today, I and KotCzarny on IR
Hi,
On 19-12-16 17:25, Icenowy Zheng wrote:
20.12.2016, 00:17, "Hans de Goede" :
Hi,
On 19-12-16 17:06, Icenowy Zheng wrote:
19.12.2016, 23:30, "Hans de Goede" :
Hi,
On 19-12-16 16:22, Icenowy Zheng wrote:
Hi everyone,
Today, I and KotCzarny on IRC of linux-s
Hi,
On 19-12-16 17:06, Icenowy Zheng wrote:
19.12.2016, 23:30, "Hans de Goede" :
Hi,
On 19-12-16 16:22, Icenowy Zheng wrote:
Hi everyone,
Today, I and KotCzarny on IRC of linux-sunxi found a problem in the SID
controller of H3 (incl. H2+).
See https://irclog.whitequark
Hi,
On 19-12-16 16:22, Icenowy Zheng wrote:
Hi everyone,
Today, I and KotCzarny on IRC of linux-sunxi found a problem in the SID
controller of H3 (incl. H2+).
See https://irclog.whitequark.org/linux-sunxi/2016-12-19 .
Two read method of the H3 eFUSE is used in the BSP: by register accessing,
Hi,
On 13-12-16 21:28, Simon Glass wrote:
Hi,
On 12 December 2016 at 19:36, Jernej Skrabec wrote:
This patch series add support for HDMI output. Support for other,
newer, SoCs, which also uses DE2 and same or similar HDMI controller
and PHY can be easily added later (A83T/A64/H5/R40). Current
Hi,
On 30-11-16 11:50, Olliver Schinagl wrote:
Hey maime,
Sorry for constantly getting your e-mail address wrong! Sorry!
On 30-11-16 10:12, maxime.rip...@free-electrons.com wrote:
On Wed, Nov 30, 2016 at 09:00:51AM +, Marcel Ziswiler wrote:
Hi Olliver
On Fri, 2016-11-25 at 16:30 +0100,
discuss this proper I guess.
On 15-11-16 10:26, Hans de Goede wrote:
Hi,
On 15-11-16 04:25, Joe Hershberger wrote:
On Tue, Nov 8, 2016 at 9:54 AM, Olliver Schinagl
wrote:
Currently we inject 5 ethernet addresses into the environment, just in
case we may need them. We do this because some boards
Hi,
On 15-11-16 11:17, Olliver Schinagl wrote:
Hey Hans,
I was hopeing and expecting this :)
As you will be able to tell below, I need to learn a bit more as to why we do
things and discuss this proper I guess.
On 15-11-16 10:26, Hans de Goede wrote:
Hi,
On 15-11-16 04:25, Joe
Hi,
On 15-11-16 04:25, Joe Hershberger wrote:
On Tue, Nov 8, 2016 at 9:54 AM, Olliver Schinagl wrote:
Currently we inject 5 ethernet addresses into the environment, just in
case we may need them. We do this because some boards have no eeprom
(programmed) with a proper ethernet address. With th
Hi,
On 14-11-16 15:11, Olliver Schinagl wrote:
Hey Hans,
On 14-11-16 12:26, Hans de Goede wrote:
Hi,
On 08-11-16 17:38, Olliver Schinagl wrote:
The current implementation to force the PHY into master mode is to have a
define which affects all realtek PHY's. This is not needed a
looks good to me:
Reviewed-by: Hans de Goede
Regards,
Hans
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F
ngepi-one.dts, which is:
+ * Copyright (C) 2016 Hans de Goede
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a)
both
this does seem to be the same die as the H3, and given
that we do not have any datasheets, I agree that just
treating the H2+ as a H3 is best for now, we can always
change h2.dtsi to actually differentiate things later.
This entire series LGTM and is:
Reviewed-by: Hans de Goede
Regards,
Hans
Hi,
On 08-11-16 19:43, Maxime Ripard wrote:
On Mon, Nov 07, 2016 at 10:24:44AM +0100, Hans de Goede wrote:
On Sun, Nov 06, 2016 at 06:54:11PM +0800, Icenowy Zheng wrote:
06.11.2016, 18:13, "Hans de Goede" :
Hi,
On 06-11-16 04:35, Chen-Yu Tsai wrote:
Hi everyone,
I spent a b
Hi,
On 06-11-16 17:53, Icenowy Zheng wrote:
06.11.2016, 22:27, "Hans de Goede" :
Hi,
On 06-11-16 12:11, Icenowy Zheng wrote:
All A33 Q8 tablets features a LCD panel, with a resolution of either
800x480 or 1024x600.
Add "bone" device nodes to the device tree.
Bon
Hi,
On 07-11-16 09:11, Maxime Ripard wrote:
Hi,
On Sun, Nov 06, 2016 at 06:54:11PM +0800, Icenowy Zheng wrote:
06.11.2016, 18:13, "Hans de Goede" :
Hi,
On 06-11-16 04:35, Chen-Yu Tsai wrote:
Hi everyone,
I spent a bit of time adding DRM support for the A23 yesterday
Hi,
On 06-11-16 12:11, Icenowy Zheng wrote:
All A33 Q8 tablets features a LCD panel, with a resolution of either
800x480 or 1024x600.
Add "bone" device nodes to the device tree.
Bone ?
Signed-off-by: Icenowy Zheng
He, as discussed in the other thread since sun8i-a33-q8-tablet.dts
is use
Hi,
On 06-11-16 11:54, Icenowy Zheng wrote:
06.11.2016, 18:13, "Hans de Goede" :
Hi,
On 06-11-16 04:35, Chen-Yu Tsai wrote:
Hi everyone,
I spent a bit of time adding DRM support for the A23 yesterday.
Icenowy successfully got DRM working for the A33 Q8 tablets.
It occu
Hi,
On 06-11-16 04:35, Chen-Yu Tsai wrote:
Hi everyone,
I spent a bit of time adding DRM support for the A23 yesterday.
Icenowy successfully got DRM working for the A33 Q8 tablets.
It occurred to me today that we have 2 types of panels for the
A33 Q8 tablets, one is 800x480 and the other is 10
Hi,
On 29-10-16 14:52, Hans de Goede wrote:
Hi,
On 21-10-16 03:24, Andre Przywara wrote:
From: Amit Singh Tomar
Mostly by adding MACH_SUN50I to some existing #ifdefs enable support
for the the HCI0 USB host controller on the A64.
Fix up some minor 64-bit hiccups on the way.
Add the bare
Hi,
On 30-10-16 06:30, Chen-Yu Tsai wrote:
On Sat, Oct 29, 2016 at 8:06 PM, Hans de Goede wrote:
Hi,
On 28-10-16 19:30, Hans de Goede wrote:
Hi Chen-Yu,
On 28-10-16 12:21, Chen-Yu Tsai wrote:
Hi everyone,
This series adds full SPL with DRAM initialization for sun9i (A80).
The bulk of
then CONFIG_USB_MAX_CONTROLLER_COUNT no longer being necessary
(it should be dropped from include/configs/sun50i.h) this patch looks
good to me and is:
Reviewed-by: Hans de Goede
Note I cannot merged it till Marek merges the first patch in
the series, which really needs to go through the u-boot
Przywara
Patch looks good to me:
Reviewed-by: Hans de Goede
Regards,
Hans
p.s.
About the ohci_writel macro changes also giving the macro parameters
more sensible names, I believe it is fine to do this while at it and
that this does not need to be split out.
---
drivers/usb/host/ohci-hcd.c
Hi,
On 21-10-16 02:11, Andre Przywara wrote:
The sun8i-emac driver works fine with the A64 Ethernet IP, but we are
missing an alias entry to trigger the driver instantiation by U-Boot.
Add the line to point U-Boot to the Ethernet DT node.
This enables TFTP boot on the Pine64.
Signed-off-by: And
Hi,
On 29-10-16 03:16, Chen-Yu Tsai wrote:
On Sat, Oct 29, 2016 at 1:30 AM, Hans de Goede wrote:
Hi Chen-Yu,
On 28-10-16 12:21, Chen-Yu Tsai wrote:
Hi everyone,
This series adds full SPL with DRAM initialization for sun9i (A80).
The bulk of the work was done by the people at Theobroma
Hi,
On 28-10-16 19:30, Hans de Goede wrote:
Hi Chen-Yu,
On 28-10-16 12:21, Chen-Yu Tsai wrote:
Hi everyone,
This series adds full SPL with DRAM initialization for sun9i (A80).
The bulk of the work was done by the people at Theobroma Systems.
Their work can be found here:
https
Hi,
On 29-10-16 13:08, Chen-Yu Tsai wrote:
On Sat, Oct 29, 2016 at 2:45 AM, Jagan Teki wrote:
On Fri, Oct 28, 2016 at 3:51 PM, Chen-Yu Tsai wrote:
From: Philipp Tomsich
On sun9i, the GTBUS manages transaction priority and bandwidth
for multiple read ports when accessing DRAM. The initialis
Hi,
On 28-10-16 20:54, Jagan Teki wrote:
On Fri, Oct 28, 2016 at 3:51 PM, Chen-Yu Tsai wrote:
From: Philipp Tomsich
This adds DRAM initialisation code for sun9i, which calculates the
appropriate timings based on timing information for the supplied
DDR3 bin and the clock speeds used.
With th
ULL before poking.
Fixes: b3e0d141ca9f (phy: sun4i: add support for A64 usb phy)
Signed-off-by: Icenowy Zheng
Acked-by: Maxime Ripard
Patch LGTM too:
Reviewed-by: Hans de Goede
Regards,
Hans
---
drivers/phy/phy-sun4i-usb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
HI,
On 26-10-16 12:14, Hans de Goede wrote:
Hi,
On 26-10-16 10:52, Icenowy Zheng wrote:
26.10.2016, 16:28, "Hans de Goede" :
Hi,
On 25-10-16 06:11, Icenowy Zheng wrote:
On some newer Allwinner SoCs (H3 or A64), the PHY0 can be either routed to
the MUSB controller (which
Hi Chen-Yu,
On 28-10-16 12:21, Chen-Yu Tsai wrote:
Hi everyone,
This series adds full SPL with DRAM initialization for sun9i (A80).
The bulk of the work was done by the people at Theobroma Systems.
Their work can be found here:
https://git.theobroma-systems.com/armadillo-u-boot.git/
I pic
Hi,
On 26-10-16 10:52, Icenowy Zheng wrote:
26.10.2016, 16:28, "Hans de Goede" :
Hi,
On 25-10-16 06:11, Icenowy Zheng wrote:
On some newer Allwinner SoCs (H3 or A64), the PHY0 can be either routed to
the MUSB controller (which is an OTG controller) or the OHCI/EHCI pair
(which
Hi,
On 25-10-16 06:11, Icenowy Zheng wrote:
On some newer Allwinner SoCs (H3 or A64), the PHY0 can be either routed to
the MUSB controller (which is an OTG controller) or the OHCI/EHCI pair
(which is a Host-only controller, but more stable and easy to implement).
This property marks whether on
Hi,
On 26-10-16 09:00, Jagan Teki wrote:
On Tue, Oct 25, 2016 at 3:59 AM, André Przywara wrote:
On 21/10/16 11:28, Hans de Goede wrote:
Hi,
On 21-10-16 12:06, Andre Przywara wrote:
Hi,
On 21/10/16 10:31, Jagan Teki wrote:
On Fri, Oct 21, 2016 at 5:41 AM, Andre Przywara
wrote:
The sun8i
Hi,
Adding Maxime Ripard to the Cc (not sure if he is in the d...@linux-sunxi.org
alias ?)
On 25-10-16 16:36, Olliver Schinagl wrote:
Hey all,
as some of you are probably aware, some users occasionally experience some
instability using the mainline components. I specifically only want to foc
Hi,
On 21-10-16 12:06, Andre Przywara wrote:
Hi,
On 21/10/16 10:31, Jagan Teki wrote:
On Fri, Oct 21, 2016 at 5:41 AM, Andre Przywara wrote:
The sun8i-emac driver works fine with the A64 Ethernet IP, but we are
missing an alias entry to trigger the driver instantiation by U-Boot.
Add the lin
Hi,
On 20-10-16 14:55, Maxime Ripard wrote:
On Thu, Oct 20, 2016 at 11:17:13AM +0200, Hans de Goede wrote:
Yes that is the idea. Although it is not really fake as theoretically
the CEC pin could be used as a general gpio. Basically the idea is that
if the hardware only offers get and set
Hi,
On 20-10-16 14:55, Maxime Ripard wrote:
On Thu, Oct 20, 2016 at 11:17:13AM +0200, Hans de Goede wrote:
Yes that is the idea. Although it is not really fake as theoretically
the CEC pin could be used as a general gpio. Basically the idea is that
if the hardware only offers get and set
s to adapter.
Maybe they will read this sysfs file. Who knows.
https://github.com/Pulse-Eight/libcec/issues/67
Thats why to make this cec driver "more independent" and I wanted to somehow
get address from EDID.
But as for now I don't think this is very important and we shouldn't
Hi,
On 19-10-16 20:33, Jarosław Nieć wrote:
On Wed, Oct 19, 2016 at 2:55 PM, Maxime Ripard mailto:maxime.rip...@free-electrons.com>> wrote:
On Wed, Oct 19, 2016 at 11:53:10AM +0200, Hans de Goede wrote:
> > > If all the hardware allows you to-do is set / re
Hi,
On 19-10-16 11:57, Chen-Yu Tsai wrote:
On Wed, Oct 19, 2016 at 5:53 PM, Hans de Goede wrote:
Hi,
On 19-10-16 05:16, Chen-Yu Tsai wrote:
On Tue, Oct 18, 2016 at 6:14 PM, Hans de Goede
wrote:
Hi,
On 17-10-16 23:33, Jarosław Nieć wrote:
Hi Maxime,
On Mon, Oct 17, 2016 at 9:51 PM
Hi,
On 19-10-16 05:16, Chen-Yu Tsai wrote:
On Tue, Oct 18, 2016 at 6:14 PM, Hans de Goede wrote:
Hi,
On 17-10-16 23:33, Jarosław Nieć wrote:
Hi Maxime,
On Mon, Oct 17, 2016 at 9:51 PM, Maxime Ripard
mailto:maxime.rip...@free-electrons.com>>
wrote:
Hi Jarosław,
On Mon,
Hi,
On 17-10-16 23:33, Jarosław Nieć wrote:
Hi Maxime,
On Mon, Oct 17, 2016 at 9:51 PM, Maxime Ripard mailto:maxime.rip...@free-electrons.com>> wrote:
Hi Jarosław,
On Mon, Oct 17, 2016 at 08:15:53PM +0200, Jarosław Nieć wrote:
> I've decided that I want to learn kernel hacking a l
Hi,
On 10/11/2016 12:21 PM, Icenowy Zheng wrote:
2016年10月11日 下午5:37于 Hans de Goede 写道：
Hi,
I have a request: could you please test this driver on your E708 Q1? (According
to the info you published on github, your E708 has also ili)
I'm afraid the touchscreen on my E708 Q1 is b
Hi,
On 10/11/2016 02:33 AM, Icenowy Zheng wrote:
This driver adds support for Ilitek ili2139 touch IC, which is used in
several Colorfly tablets (for example, Colorfly E708 Q1, which is an
Allwinner A31s tablet with mainline kernel support).
Theortically it may support more Ilitek touch ICs, ho
Hi,
On 19-09-16 18:07, TsvetanUsunov wrote:
Hi,
We make our final touch of A64-OLinuXino PCB and there we add option eMMC Flash
to work on dual voltages 1.8V and 3.3V.
The eMMC is connected to AXP803 pin.34 GPIO1/LDO. The problem is that when A64
boots and AXP803 is not initialized it outputs
Hi,
On 09-09-16 21:13, Pantelis Antoniou wrote:
Hi Hans,
On Sep 1, 2016, at 22:08 , Hans de Goede wrote:
Allwinnner A13 / A23 / A33 based Q8 tablets are popular cheap 7" tablets
of which a new batch is produced every few weeks. Each batch uses a
different mix of touchscreen, accelero
Hi,
On 09-09-16 23:41, Rob Herring wrote:
On Thu, Sep 1, 2016 at 2:08 PM, Hans de Goede wrote:
Allwinnner A13 / A23 / A33 based Q8 tablets are popular cheap 7" tablets
of which a new batch is produced every few weeks. Each batch uses a
different mix of touchscreen, accelerometer and
Hi,
On 06-09-16 17:31, wens Tsai wrote:
On Tue, Sep 6, 2016 at 7:28 PM, Hans de Goede wrote:
Hi,
On 06-09-16 13:02, wens Tsai wrote:
Hi Hans,
I've built the latest sunxi-next branches of Linux and U-boot and
tried it on my Q8 A23 tablet. My tablet has an OTG adapter with a
USB eth
Hi,
On 06-09-16 13:02, wens Tsai wrote:
Hi Hans,
I've built the latest sunxi-next branches of Linux and U-boot and
tried it on my Q8 A23 tablet. My tablet has an OTG adapter with a
USB ethernet adapter connected all the time. Upon booting into
Linux I get an endless stream of:
musb_bus_sus
Hi,
On 04-09-16 14:48, Saurabh Jain wrote:
Is there a straightforward way to convert a script.bin file to a device tree
file? Any HOWTO that maps the various options?
Should I first be experimenting with the sunxi Uboot instead of Mainline?
My device has an AXP152 paired with an A20. Looking
Hi,
On 02-09-16 13:13, Saurabh Jain wrote:
Hey Hans, thanks for your response.
There might be an otg header on the PCB ?
None that is obvious. I am currently looking at the A20 datasheet and trying to
trace the OTG pin... but with a BGA chip that is hard.
Otherwise you can install
Hi,
On 02-09-16 08:14, Saurabh Jain wrote:
Hello Everyone!
Thanks for all your excellent work on AllWinner processors. Thanks to your
work, I have been able to do interesting things with the CubieBoards I have.
I have recently received an AllWinner A20 based device. I've been following the
s
m-$(CONFIG_LKDTM) += lkdtm_bugs.o
diff --git a/drivers/misc/q8-hardwaremgr.c b/drivers/misc/q8-hardwaremgr.c
new file mode 100644
index 000..e75625e
--- /dev/null
+++ b/drivers/misc/q8-hardwaremgr.c
@@ -0,0 +1,512 @@
+/*
+ * Allwinner q8 formfactor tablet hardware manager
+ *
+ * Copyright
Hi All,
Here is a first RFC for the q8 tablet hw-manager I've been talking
about for a while now.
The touchscreen part is finished, I'll start working on the
accelerometer bits next.
Note that this requires the "of: changesets: Introduce changeset
helper methods" patch from Pantelis. If that is
Hi,
On 31-08-16 18:22, Maxime Ripard wrote:
On Mon, Aug 29, 2016 at 10:18:32PM +0800, Icenowy Zheng wrote:
UART1 is connected to the bluetooth part of RTL8723BS WiFi/BT combo card
on iNet D978 Rev2 board.
Enable the UART1 to make it possible to use the modified hciattach by
Realtek to drive th
Hi,
On 10-08-16 13:51, LABBE Corentin wrote:
On Wed, Aug 10, 2016 at 11:54:37AM +0200, Hans de Goede wrote:
Hi Labbe,
Since your ethernet driver is more or less ready for merging,
I was wondering what the status of external phy support is ?
I've a bunch of H3 boards (all orangepi-s)
Hi,
On 19-08-16 13:40, Jens Kuske wrote:
The H3 PLL5 used for DRAM barely manages to lock to the required
frequency before DRAM controller starts, sometimes leading to wrong
delay-line calibration results.
This patch changes the PLL tuning parameters to the same values as
boot0 used, which speed
Hi,
On 18-08-16 13:57, Icenowy Zheng wrote:
18.08.2016, 17:26, "Hans de Goede" :
Hi,
On 18-08-16 05:57, Icenowy Zheng wrote:
Hi Hans,
I currently found my old 9.7" A33 tablet, which has no brand (directly bought
in the markets in Shenzhen).
It has 16GB NAND (dual Hynix
Hi,
On 18-08-16 05:57, Icenowy Zheng wrote:
Hi Hans,
I currently found my old 9.7" A33 tablet, which has no brand (directly bought
in the markets in Shenzhen).
It has 16GB NAND (dual Hynix 8GB NAND chips), 1GB RAM, a 9.7" LVDS
screen(1024x768, IPS, good display quality among Allwinner tablets
Hi,
On 12-08-16 13:46, LABBE Corentin wrote:
Add the hwspinlock device tree node for the device present on H3.
Signed-off-by: LABBE Corentin
---
arch/arm/boot/dts/sun8i-h3.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/
Hi Labbe,
Since your ethernet driver is more or less ready for merging,
I was wondering what the status of external phy support is ?
I've a bunch of H3 boards (all orangepi-s) which use an external
phy, if I take your v2 driver then what is needed on top to
get the ethernet to work on these ?
T
Hi All,
Recently I've been working on getting the sdio-wifi, found on
many a23 / a33 tablets as well as on some a10s hdmi sticks and
on various h3 SBCs such as the Orange Pi, to work with the
mainline kernel.
If you use my sunxi-wip kernel branch (which has some dts bits
to enable this as well a
Hi,
On 01-08-16 15:52, Jean-Francois Moine wrote:
On Sat, 30 Jul 2016 12:19:03 +0200
Hans de Goede wrote:
Jean-Francois, can you submit a v2 of your patch and make the writing of
SDXC_REG_NTSR depend on a new sun8i-a83t-mmc compatible ?
Also you should probably drop the bits about the clock
Hi,
On 29-07-16 21:17, Maxime Ripard wrote:
On Thu, Jul 21, 2016 at 11:26:55AM +0200, Jean-Francois Moine wrote:
On Thu, 21 Jul 2016 10:56:15 +0200
Maxime Ripard wrote:
On Wed, Jul 20, 2016 at 08:16:28PM +0200, Jean-Francois Moine wrote:
The 'new timing mode' with 8 bits DDR works correctly
Hi,
On 13-06-16 09:40, Maxime Ripard wrote:
On Thu, Jun 09, 2016 at 10:34:40AM +0200, Hans de Goede wrote:
Hi,
On 09-06-16 09:53, Maxime Ripard wrote:
Hi Hans,
On Sat, Jun 04, 2016 at 08:10:54PM +0200, Hans de Goede wrote:
Hi All,
As part of testing that my "ARM: dts: sun5i: Move di
Hi,
On 10-07-16 23:13, Steven Saunderson wrote:
Hi,
I have an A33 powered tablet (10" PendoPad) and I'm trying to get it to boot
from SD card. I'd like to change this Android box into a Linux box.
I'm using the latest U-Boot with settings from the A33 configs that are supplied. I have a
mo
Hi,
On 05-07-16 08:54, Maxime Ripard wrote:
On Thu, Jun 30, 2016 at 11:45:00AM +0200, Hans de Goede wrote:
Hi,
On 29-06-16 22:38, Maxime Ripard wrote:
Hi,
On Wed, Jun 29, 2016 at 08:46:59PM +0200, Hans de Goede wrote:
The auxtek t004 has its otg usb vbus hardwired to 5v (likely in case
Hi,
On 04-07-16 04:35, Icenowy Zheng wrote:
04.07.2016, 06:03, "Hans de Goede" :
Hi,
On 21-06-16 11:46, Hans de Goede wrote:
Hi,
On 21-06-16 01:54, Icenowy Zheng wrote:
The GSLX680_D86_FW can give out the right status with silead.ko.
(But how can the wrong firmware work i
Hi,
On 21-06-16 11:46, Hans de Goede wrote:
Hi,
On 21-06-16 01:54, Icenowy Zheng wrote:
The GSLX680_D86_FW can give out the right status with silead.ko.
(But how can the wrong firmware work in the same way as the correct one?!
The firmware file is not really firmware, I believe it contains
Hi All,
Between my $dayjob, linux-sunxi, other foss projects and last but
not least spending time with my wife and children I'm way too
busy lately.
So I've decided to seriously scale back my involvement in
linux-sunxi. I will still finish all the things I've pending
for merging upstream + some
Hi,
On 03-07-16 16:04, Karsten Merker wrote:
Hello,
I am experiencing a kernel panic on shutdown due to killing init
on various Allwinner A20-based systems (e.g. Cubietruck and
Lime2). Killing init in turn appears to be a result of a locked
i2c bus. This only happens on shutdown, but not on reb
Hi,
On 30-06-16 07:47, Kishon Vijay Abraham I wrote:
Hi,
On Wednesday 29 June 2016 11:44 PM, Hans de Goede wrote:
Hi Kishon,
The "USB: Fix of_usb_get_dr_mode_by_phy with a shared phy block"
patch on which this series depends is in usb-next now:
https://git.kernel.org/cgit/linux/
Hi,
On 13-06-16 18:13, Olliver Schinagl wrote:
Commit b19236fd1 ("sunxi: Increase SPL header size to 64 bytes to avoid
code corruption") Added defines for MMC0 and SPI as boot identification.
After verifying on an OLinuXino Lime2 with NAND and eMMC, the expected
values have been confirmed and ad
HI,
On 01-07-16 02:47, Rob Herring wrote:
On Thu, Jun 23, 2016 at 11:33:27AM +0200, Hans de Goede wrote:
Hi,
On 23-06-16 00:25, Rob Herring wrote:
On Wed, Jun 22, 2016 at 12:59 PM, Hans de Goede wrote:
Some devices need a while to boot their firmware after providing clks /
de-asserting
Hi,
On 30-06-16 12:18, Jonas Gorski wrote:
Hi,
On 30 June 2016 at 12:04, Hans de Goede wrote:
Hi,
On 30-06-16 11:58, Kalle Valo wrote:
Hans de Goede writes:
Hi,
On 30-06-16 11:02, Kalle Valo wrote:
Priit Laes writes:
What is the size of this nvram file? As it's board specif
Hi,
On 30-06-16 11:58, Kalle Valo wrote:
Hans de Goede writes:
Hi,
On 30-06-16 11:02, Kalle Valo wrote:
Priit Laes writes:
What is the size of this nvram file? As it's board specific, I wonder
if we can simply include it inside of the DT verbatim. I remember
doing that (in the pr
Hi,
On 29-06-16 20:51, 'Arend Van Spriel' via linux-sunxi wrote:
On 29-6-2016 20:01, Hans de Goede wrote:
Hi,
On 29-06-16 19:00, Kalle Valo wrote:
Hans de Goede writes:
Hi,
On 29-06-16 16:42, Jonas Gorski wrote:
Hi,
On 29 June 2016 at 16:04, Hans de Goede wrote:
Hi,
On 30-06-16 11:02, Kalle Valo wrote:
Priit Laes writes:
What is the size of this nvram file? As it's board specific, I wonder
if we can simply include it inside of the DT verbatim. I remember
doing that (in the pre-dtb days, on real open firmware) for the
"spidernet"
ethernet driver.
It
Hi,
On 30-06-16 10:46, Kalle Valo wrote:
Arend Van Spriel writes:
Since we are dealing with a per-board config-file here, which is
loaded from the os filesystem we really need to specify a basename
here as the list of possible boards is endless, so we cannot
have a lookup table in the driver.
Hi,
On 29-06-16 22:38, Maxime Ripard wrote:
Hi,
On Wed, Jun 29, 2016 at 08:46:59PM +0200, Hans de Goede wrote:
The auxtek t004 has its otg usb vbus hardwired to 5v (likely in case
people use it to power the board instead of the dedicated power micro
usb connector), it does have an id pin, so
The a10s mk802 uses a rtl8189es sdio wifi chip, add a node enabling
the mmc1 controller, this enables using the wifi chip (together with
an out of tree sdio driver for it).
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun5i-a10s-mk802.dts | 9 +
1 file changed, 9 insertions
The auxtek t004 has its otg usb vbus hardwired to 5v (likely in case
people use it to power the board instead of the dedicated power micro
usb connector), it does have an id pin, so it allows full otg
functionality.
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
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