Hi,
On 09/01/20 3:24 PM, Corentin Labbe wrote:
> Hello
>
> On next-20200108 (at least), the sunxi_ahci fail to probe with:
> 3.025955] 8<--- cut here ---
> [3.029012] Unable to handle kernel NULL pointer dereference at virtual
> address 0071
> [3.037115] pgd = (ptrval)
> [
Hi,
On 24/10/19 4:24 PM, Ondrej Jirman wrote:
> From: Icenowy Zheng
>
> Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
> controlled).
>
> Add a driver for it.
>
> The register operations in this driver is mainly extracted from the BSP
> USB3 driver.
>
> Signed-off-by:
On 15/04/19 4:47 PM, Paul Kocialkowski wrote:
> Hi,
>
> Le jeudi 14 mars 2019 à 14:05 +0100, Paul Kocialkowski a écrit :
>> On platforms where the MUSB and HCI controllers share PHY0, PHY passby
>> is required when using the HCI controller with the PHY, but it must be
>> disabled when the MUSB
Hi,
On 14/11/18 10:27 AM, Icenowy Zheng wrote:
在 2018-10-04四的 20:28 +0800,Icenowy Zheng写道:
Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
controlled).
Add a driver for it.
The register operations in this driver is mainly extracted from the
BSP
USB3 driver.
Signed-off-by:
On 02/11/18 2:11 PM, Icenowy Zheng wrote:
> 在 2018-10-04四的 20:28 +0800,Icenowy Zheng写道:
>> The USB 2.0 PHY on Allwinner H6 SoC is similar to older Allwinner
>> SoCs,
>> with some USB0 quirk like A83T and PHY index 1/2 missing.
>>
>> Add support for it.
>>
>> Signed-off-by: Icenowy Zheng
>>
Hi,
On Thursday 15 March 2018 11:47 AM, Chen-Yu Tsai wrote:
> Hi Kishon,
>
> On Fri, Feb 16, 2018 at 7:20 PM, Kishon Vijay Abraham I <kis...@ti.com> wrote:
>>
>>
>> On Friday 19 January 2018 08:15 PM, Maxime Ripard wrote:
>>> On Fri, Jan 19, 20
On Friday 19 January 2018 08:15 PM, Maxime Ripard wrote:
> On Fri, Jan 19, 2018 at 05:25:41PM +0800, Chen-Yu Tsai wrote:
>> The AXP223 PMIC, like the AXP221, does not generate VBUS change
>> interrupts when N_VBUSEN is used to drive VBUS for the OTG port
>> on the board.
>>
>> This was not
On Friday 19 January 2018 01:43 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Friday 19 January 2018 11:55 AM, Chen-Yu Tsai wrote:
>> Hi Kishon,
>>
>> On Mon, Jan 15, 2018 at 11:06 PM, Hermann Lauer
>> <hermann.la...@iwr.uni-heidelberg.de> wrote:
>&
Hi,
On Friday 19 January 2018 11:55 AM, Chen-Yu Tsai wrote:
> Hi Kishon,
>
> On Mon, Jan 15, 2018 at 11:06 PM, Hermann Lauer
> wrote:
>> On Wed, Jan 03, 2018 at 04:49:44PM +0800, Icenowy Zheng wrote:
>>> Allwinner R40 features a USB PHY like the one in A64,
Hi,
On Saturday 30 December 2017 05:08 PM, Icenowy Zheng wrote:
> 在 2017年10月18日星期三 CST 下午7:46:08,Kishon Vijay Abraham I 写道:
>> On Wednesday 18 October 2017 05:12 PM, Maxime Ripard wrote:
>>> On Wed, Oct 18, 2017 at 05:09:00PM +0530, Kishon Vijay Abraham I wrote:
>>>&g
Hi,
On Tuesday 10 October 2017 02:28 AM, Maxime Ripard wrote:
> On Sun, Oct 08, 2017 at 04:29:01AM +, Icenowy Zheng wrote:
>> Allwinner R40 features a USB PHY like the one in A64, but with 3 PHYs.
>>
>> Add support for it.
>>
>> Signed-off-by: Icenowy Zheng
>
> Acked-by:
Hi Icenowy,
On Thursday 28 September 2017 09:03 PM, Maxime Ripard wrote:
> On Thu, Sep 28, 2017 at 09:58:59AM +, icen...@aosc.io wrote:
>> 在 2017-09-28 17:47,Maxime Ripard 写道:
>>> On Thu, Sep 28, 2017 at 09:33:48AM +, Icenowy Zheng wrote:
Allwinner V3s SoC has only one USB PHY, but
Hi,
On Thursday 17 August 2017 10:35 PM, Chen-Yu Tsai wrote:
> On Fri, Aug 11, 2017 at 1:08 AM, Rob Herring wrote:
>> On Thu, Aug 03, 2017 at 04:14:04PM +0800, Chen-Yu Tsai wrote:
>>> The Allwinner H3 SoC has 4 USB PHYs, so it needs four sets of pmu
>>> regions, clocks, resets,
On Thursday 03 August 2017 01:44 PM, Chen-Yu Tsai wrote:
> The Allwinner H3 SoC has 4 USB PHYs, so it needs four sets of pmu
> regions, clocks, resets, and optional vbus properties. These were
> not described when the H3 compatible string was added.
>
> Fixes: 626a630e003c ("phy-sun4i-usb: Add
gt; MMIO region is needed.
>
> In order to prevent device tree compatibility breakage, add this region in
> 4.11.
I feel the binding documentation can go along with the dt changes. Moreover I
have no plans of sending another pull request for this -rc cycle.
FWIW:
Acked-by: Kishon Vijay
OHCI pair, it will needs a "pmu0" regs to
> tweak, like other EHCI/OHCI pairs in Allwinner SoCs.
>
> Add this to the binding of USB PHYs on Allwinner H3/V3s/A64.
>
> Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
> Acked-by: Chen-Yu Tsai <w...@csi
On Wednesday 05 April 2017 12:33 PM, Maxime Ripard wrote:
> On Wed, Apr 05, 2017 at 02:45:16AM +0800, Icenowy Zheng wrote:
>> Allwinner A64 SoC features a switchable PHY0 like the one in H3, which
>> can switch between a MUSB controller and a pair of OHCI/EHCI controller.
>>
>> Enable PHY0 route
On Saturday 25 March 2017 08:20 PM, Icenowy Zheng wrote:
> Allwinner H3 have a its USB PHY0 routed to two USB controllers: one is
> a MUSB controller, which can work in peripheral mode, but works badly in
> host mode (several hardware will fail on the MUSB controller, even connect
> one MUSB
On Friday 28 October 2016 11:45 PM, Hans de Goede wrote:
> Hi,
>
> On 28-10-16 18:27, Icenowy Zheng wrote:
>> Allwinner SoC's PHY 0, when used as OTG controller, have no pmu part.
>> The code that poke some unknown bit of PMU for H3/A64 didn't check
>> the PHY, and will cause kernel oops when
On Sunday 03 July 2016 01:38 AM, Hans de Goede wrote:
> Hi,
>
> On 30-06-16 07:47, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Wednesday 29 June 2016 11:44 PM, Hans de Goede wrote:
>>> Hi Kishon,
>>>
>>> The "USB: Fix of_usb_get
Hi,
On Wednesday 29 June 2016 11:44 PM, Hans de Goede wrote:
> Hi Kishon,
>
> The "USB: Fix of_usb_get_dr_mode_by_phy with a shared phy block"
> patch on which this series depends is in usb-next now:
>
>
Hi,
On Sunday 22 November 2015 04:59 PM, Hans de Goede wrote:
> From: Reinder de Haan
>
> Note this commit only adds support for phys 1-3, phy 0, the otg phy, is
> not yet (fully) supported after this commit.
>
> Signed-off-by: Reinder de Haan
>
Hi,
On Friday 31 July 2015 01:31 PM, Hans de Goede wrote:
sun4i_usb_phy_set_squelch_detect is used by other code, which may be built
as a module, so it should be exported.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
Changes in v6:
-New patch in v6 of the sunxi musb support series
Hi,
On Wednesday 08 July 2015 08:11 PM, Hans de Goede wrote:
sun4i_usb_phy_set_squelch_detect is used by other code, which may be built
as a module, so it should be exported.
Signed-off-by: Hans de Goede hdego...@redhat.com
merged this patch to linux-phy tree.
Cheers
Kishon
---
Changes
Hi,
On Saturday 13 June 2015 06:07 PM, Hans de Goede wrote:
Hi Kishon,
Here is a patch series with all my oustanding phy-sun4i-usb changes pending
for merging into 4.3.
This includes the 5th iteration of the OTG support addition, now with the
extcon provider support addition split-out
On Wednesday 15 July 2015 04:25 PM, Kishon Vijay Abraham I wrote:
Hi,
On Sunday 31 May 2015 09:40 PM, Hans de Goede wrote:
The usb0 phy is connected to an OTG controller, and as such needs some
special
handling:
1) It allows explicit control over the pullups, enable these on phy_init
Hi,
On Sunday 31 May 2015 09:40 PM, Hans de Goede wrote:
The usb0 phy is connected to an OTG controller, and as such needs some special
handling:
1) It allows explicit control over the pullups, enable these on phy_init and
disable them on phy_exit.
2) It has bits to signal id and vbus
Hi,
On Wednesday 08 July 2015 08:11 PM, Hans de Goede wrote:
sun4i_usb_phy_set_squelch_detect is used by other code, which may be built
as a module, so it should be exported.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
Changes in v6:
-New patch in v6 of the sunxi musb support
Hi,
On Saturday 13 June 2015 06:07 PM, Hans de Goede wrote:
Hi Kishon,
Here is a patch series with all my oustanding phy-sun4i-usb changes pending
for merging into 4.3.
This includes the 5th iteration of the OTG support addition, now with the
extcon provider support addition split-out into a
Hi,
On Sunday 31 May 2015 09:40 PM, Hans de Goede wrote:
The usb0 phy is connected to an OTG controller, and as such needs some special
handling:
1) It allows explicit control over the pullups, enable these on phy_init and
disable them on phy_exit.
2) It has bits to signal id and vbus detect
Hi,
On Thursday 11 June 2015 03:23 PM, Hans de Goede wrote:
Hi,
On 11-06-15 11:42, Kishon Vijay Abraham I wrote:
Hi,
On Sunday 31 May 2015 09:40 PM, Hans de Goede wrote:
The usb0 phy is connected to an OTG controller, and as such needs some special
handling:
1) It allows explicit control
On Thursday 11 June 2015 06:05 PM, Hans de Goede wrote:
Hi,
On 11-06-15 13:16, Kishon Vijay Abraham I wrote:
Hi,
On Thursday 11 June 2015 03:23 PM, Hans de Goede wrote:
Hi,
On 11-06-15 11:42, Kishon Vijay Abraham I wrote:
Hi,
On Sunday 31 May 2015 09:40 PM, Hans de Goede wrote
+Chanwoo
Hi,
On Sunday 31 May 2015 09:40 PM, Hans de Goede wrote:
The usb0 phy is connected to an OTG controller, and as such needs some special
handling:
1) It allows explicit control over the pullups, enable these on phy_init and
disable them on phy_exit.
2) It has bits to signal id and
along with the other patch in the series. So I think it's
better you take this series along with the musb sunxi patch series.
Acked-by: Kishon Vijay Abraham I kis...@ti.com
Thanks
Kishon
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Hi Felipe,
On Monday 11 May 2015 11:43 PM, Hans de Goede wrote:
Hi,
On 11-05-15 17:55, Felipe Balbi wrote:
Hi,
On Sun, May 10, 2015 at 12:02:54PM +0200, Hans de Goede wrote:
Hi,
On 08-05-15 18:06, Felipe Balbi wrote:
Hi,
On Sun, Mar 29, 2015 at 12:50:46PM +0200, Hans de Goede wrote:
The
Hi,
On Tuesday 10 March 2015 04:33 PM, Hans de Goede wrote:
Hi,
On 10-03-15 11:53, Kishon Vijay Abraham I wrote:
Hi,
On Tuesday 10 March 2015 03:43 PM, Hans de Goede wrote:
Hi,
On 10-03-15 09:57, Arnd Bergmann wrote:
On Tuesday 10 March 2015 09:04:43 Hans de Goede wrote:
Hi,
On 09-03-15
Hi,
On Wednesday 11 March 2015 06:33 PM, Hans de Goede wrote:
Hi,
On 11-03-15 13:50, Kishon Vijay Abraham I wrote:
Hi,
On Wednesday 11 March 2015 05:09 PM, Hans de Goede wrote:
Hi,
On 11-03-15 10:13, Kishon Vijay Abraham I wrote:
Hi,
On Tuesday 10 March 2015 04:33 PM, Hans de Goede wrote
Hi,
On Wednesday 11 March 2015 05:09 PM, Hans de Goede wrote:
Hi,
On 11-03-15 10:13, Kishon Vijay Abraham I wrote:
Hi,
On Tuesday 10 March 2015 04:33 PM, Hans de Goede wrote:
Hi,
On 10-03-15 11:53, Kishon Vijay Abraham I wrote:
Hi,
On Tuesday 10 March 2015 03:43 PM, Hans de Goede wrote
Hi,
On Tuesday 10 March 2015 03:43 PM, Hans de Goede wrote:
Hi,
On 10-03-15 09:57, Arnd Bergmann wrote:
On Tuesday 10 March 2015 09:04:43 Hans de Goede wrote:
Hi,
On 09-03-15 22:47, Arnd Bergmann wrote:
On Monday 09 March 2015 21:40:15 Hans de Goede wrote:
+void
On Wednesday 14 May 2014 11:18 AM, Kishon Vijay Abraham I wrote:
Hi,
On Tuesday 13 May 2014 09:14 PM, Maxime Ripard wrote:
Move the phy initialization and variables declaration to the loop itself,
since
it is where it really belongs. Also remove all the temporary variables, we
can
use
Hi,
On Tuesday 13 May 2014 09:14 PM, Maxime Ripard wrote:
Move the phy initialization and variables declaration to the loop itself,
since
it is where it really belongs. Also remove all the temporary variables, we can
use the structure members directly.
Signed-off-by: Maxime Ripard
, and
the usb host drivers left in perpetual probe deferral on my Cubietruck.
Adding an else section fixes this.
Good catch, fixed this in the sunxi-devel branch for now (until Maxime sends
a new version).
so I wont be taking this patch in my tree. Anyway FWIW
Acked-by: Kishon Vijay Abraham
Hi,
On Wednesday 07 May 2014 09:20 AM, Maxime Ripard wrote:
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while the older ones were
having
a single clock for all the phys.
Signed-off-by: Maxime Ripard
On Tuesday 04 March 2014 10:33 PM, Hans de Goede wrote:
Hi,
On 03/03/2014 02:18 PM, Kishon Vijay Abraham I wrote:
Hi,
On Sunday 02 March 2014 12:49 AM, Hans de Goede wrote:
Hi,
On 03/01/2014 06:37 PM, Kishon Vijay Abraham I wrote:
Hi,
On Saturday 01 March 2014 10:39 PM, Hans de Goede
Hi,
On Sunday 02 March 2014 12:49 AM, Hans de Goede wrote:
Hi,
On 03/01/2014 06:37 PM, Kishon Vijay Abraham I wrote:
Hi,
On Saturday 01 March 2014 10:39 PM, Hans de Goede wrote:
The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
through a single set of registers
Hi,
On Saturday 01 March 2014 10:39 PM, Hans de Goede wrote:
The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
through a single set of registers. Besides this there are also some other
phy related bits which need poking, which are per phy, but shared between the
ohci and
On Wednesday 15 January 2014 04:28 AM, Hans de Goede wrote:
The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
through a single set of registers. Besides this there are also some other
phy related bits which need poking, which are per phy, but shared between the
ohci and
Hi,
On Wednesday 15 January 2014 09:18 PM, Hans de Goede wrote:
Hi,
On 01/15/2014 04:00 PM, Kishon Vijay Abraham I wrote:
On Wednesday 15 January 2014 04:28 AM, Hans de Goede wrote:
The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
through a single set of registers
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