On Tue, 18 Oct 2016, Chen-Yu Tsai wrote:
> Revert the commit for now. clocksource_mmio_init can be made to pass back
> a pointer, but the code churn and usage of an inner struct might not be
> worth it.
You can avoid the churn by making clocksurce_mmio_init() a wrapper around a
new function, which
On Wed, 19 Mar 2014, Maxime Ripard wrote:
> On Wed, Mar 19, 2014 at 12:13:56PM +0100, Thomas Gleixner wrote:
> > On Sat, 15 Mar 2014, Carlo Caione wrote:
> >
> > > Allwinner A20/A31 SoCs have a special interrupt controller for managing
> > > NMI.
> > &
On Sat, 15 Mar 2014, Carlo Caione wrote:
> Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI.
> Three register are present to (un)mask, control and acknowledge NMI.
> These two patches add a new irqchip driver in cascade with GIC.
If I get an ack for the DT parts, I'll p
On Thu, 13 Mar 2014, Hans de Goede wrote:
> Since sun4i and sun5i are single core SOCs there is no need to mask non
> oneshot IRQs, to achieve this we use handle_fasteoi_irq with a dummy eoi.
This is slightly wrong :)
Even on a SMP system there is no need to mask the interrupt when the
controlle
On Thu, 13 Mar 2014, Hans de Goede wrote:
> On 03/13/2014 03:46 PM, Thomas Gleixner wrote:
> >> static int sun4i_irq_map(struct irq_domain *d, unsigned int virq,
> >> irq_hw_number_t hw)
> >> {
> >> - irq_set
On Wed, 12 Mar 2014, Hans de Goede wrote:
> The ENMI needs to have the ack done *after* clearing the interrupt source,
> otherwise we will get a spurious interrupt for each real interrupt. Switch
> to the new handle_fasteoi_late_irq handler which gives us the desired
> behavior.
>
> Signed-off-b
On Thu, 13 Mar 2014, Maxime Ripard wrote:
> On Wed, Mar 12, 2014 at 06:17:07PM +0100, Hans de Goede wrote:
> > The ENMI needs to have the ack done *after* clearing the interrupt source,
> > otherwise we will get a spurious interrupt for each real interrupt. Switch
> > to the new handle_fasteoi_lat
On Fri, 7 Feb 2014, Carlo Caione wrote:
> Yeah, no really difference between threaded and non threaded.
> For the record, from a mail exchange with Allwinner's engineers: "the
> NMI module is a signal conversion module. It catches the NMI pin's
> state and generates irq to GIC", so GIC does not rea
On Fri, 7 Feb 2014, Carlo Caione wrote:
> The context and the rationale is fully explained in this thread
> http://www.spinics.net/lists/arm-kernel/msg299952.html and some
> answers are already given along the thread especially by Hans here
> http://www.spinics.net/lists/arm-kernel/msg303542.html
>
On Thu, 6 Feb 2014, Carlo Caione wrote:
> On Thu, Feb 6, 2014 at 10:14 PM, Thomas Gleixner wrote:
> > On Thu, 6 Feb 2014, Carlo Caione wrote:
> >
> >> Several irqchip drivers require the level-triggered interrupt to be
> >> acked before unmasking to avoid that
On Thu, 6 Feb 2014, Carlo Caione wrote:
> Several irqchip drivers require the level-triggered interrupt to be
> acked before unmasking to avoid that a second interrupt is immediately
> triggered. This small patch introduces a new irqchip flags that is used
> to ack the IRQ line before it is unmask
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