The V3s pin controller doesn't have the bank 0 (starts at address
0x200), which is like A33. However, this is not workarounded when
developing the driver, which makes IRQ not working.
Fix the IRQ bank base.
Fixes: 56d9e4a76039 ("pinctrl: sunxi: add driver for V3s SoC")
Cc: sta...@vger.kernel.org
On Tue, Aug 1, 2017 at 10:54 PM, Icenowy Zheng wrote:
> The V3s pin controller doesn't have the bank 0 (starts at address
> 0x200), which is like A33. However, this is not workarounded when
was not worked around
"Work around" is a verb phrase. "Workarou
在 2017-08-04 10:23,Chen-Yu Tsai 写道:
On Tue, Aug 1, 2017 at 10:54 PM, Icenowy Zheng wrote:
The V3s pin controller doesn't have the bank 0 (starts at address
0x200), which is like A33. However, this is not workarounded when
was not worked around
"Work