From: Marcus Cooper <codekip...@gmail.com>
The HDMI driver has been copied from the I2S driver
and very little effort has been made to remove the
unneeded parts. Therefore the registers that are
used by the I2S hardware block are simply renamed
and they serve no purpose in providing a functioning
driver.
This patch removes the main header file and all of the
register accesses that are referenced.
Signed-off-by: Marcus Cooper <codekip...@gmail.com>
---
sound/soc/sunxi/hdmiaudio/sunxi-hdmiaudio.c | 430 ++--------------------------
sound/soc/sunxi/hdmiaudio/sunxi-hdmiaudio.h | 303 --------------------
sound/soc/sunxi/hdmiaudio/sunxi-hdmipcm.c | 1 -
sound/soc/sunxi/hdmiaudio/sunxi-sndhdmi.c | 2 -
4 files changed, 18 insertions(+), 718 deletions(-)
delete mode 100644 sound/soc/sunxi/hdmiaudio/sunxi-hdmiaudio.h
diff --git a/sound/soc/sunxi/hdmiaudio/sunxi-hdmiaudio.c
b/sound/soc/sunxi/hdmiaudio/sunxi-hdmiaudio.c
index c3b4beb..9951b63 100644
--- a/sound/soc/sunxi/hdmiaudio/sunxi-hdmiaudio.c
+++ b/sound/soc/sunxi/hdmiaudio/sunxi-hdmiaudio.c
@@ -34,11 +34,6 @@
#include <plat/sys_config.h>
#include <plat/dma_compat.h>
-#include "sunxi-hdmiaudio.h"
-
-//save the register value
-static int regsave[8];
-
static struct sunxi_dma_params sunxi_hdmiaudio_pcm_stereo_out = {
.client.name = "HDMIAUDIO PCM Stereo out",
#if defined CONFIG_ARCH_SUN4I || defined CONFIG_ARCH_SUN5I
@@ -47,219 +42,13 @@ static struct sunxi_dma_params
sunxi_hdmiaudio_pcm_stereo_out = {
.dma_addr = 0,
};
-struct sunxi_hdmiaudio_info sunxi_hdmiaudio;
-
-//clock handle
-static struct clk *hdmiaudio_apbclk;
-static struct clk *hdmiaudio_pll2clk;
-static struct clk *hdmiaudio_pllx8;
-static struct clk *hdmiaudio_moduleclk;
-
void sunxi_snd_txctrl_hdmiaudio(struct snd_pcm_substream *substream, int on)
{
- u32 reg_val;
-
- reg_val = readl(sunxi_hdmiaudio.regs + SUNXI_TXCHSEL);
- reg_val &= ~0x7;
- reg_val |= SUNXI_TXCHSEL_CHNUM(substream->runtime->channels);
- writel(reg_val, sunxi_hdmiaudio.regs + SUNXI_TXCHSEL);
-
- reg_val = readl(sunxi_hdmiaudio.regs + SUNXI_TXCHMAP);
- reg_val = 0;
- if(substream->runtime->channels == 1) {
- reg_val = 0x76543200;
- } else {
- reg_val = 0x76543210;
- }
- writel(reg_val, sunxi_hdmiaudio.regs + SUNXI_TXCHMAP);
-
- reg_val = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
- reg_val &= ~SUNXI_HDMIAUDIOCTL_SDO3EN;
- reg_val &= ~SUNXI_HDMIAUDIOCTL_SDO2EN;
- reg_val &= ~SUNXI_HDMIAUDIOCTL_SDO1EN;
- reg_val &= ~SUNXI_HDMIAUDIOCTL_SDO0EN;
- switch(substream->runtime->channels) {
- case 1:
- case 2:
- reg_val |= SUNXI_HDMIAUDIOCTL_SDO0EN; break;
- case 3:
- case 4:
- reg_val |= SUNXI_HDMIAUDIOCTL_SDO0EN |
SUNXI_HDMIAUDIOCTL_SDO1EN; break;
- case 5:
- case 6:
- reg_val |= SUNXI_HDMIAUDIOCTL_SDO0EN |
SUNXI_HDMIAUDIOCTL_SDO1EN | SUNXI_HDMIAUDIOCTL_SDO2EN; break;
- case 7:
- case 8:
- reg_val |= SUNXI_HDMIAUDIOCTL_SDO0EN |
SUNXI_HDMIAUDIOCTL_SDO1EN | SUNXI_HDMIAUDIOCTL_SDO2EN |
SUNXI_HDMIAUDIOCTL_SDO3EN; break;
- default:
- reg_val |= SUNXI_HDMIAUDIOCTL_SDO0EN; break;
- }
- writel(reg_val, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
-
- //flush TX FIFO
- reg_val = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOFCTL);
- reg_val |= SUNXI_HDMIAUDIOFCTL_FTX;
- writel(reg_val, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOFCTL);
-
- //clear TX counter
- writel(0, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOTXCNT);
-
- if (on) {
- /* hdmiaudio TX ENABLE */
- reg_val = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
- reg_val |= SUNXI_HDMIAUDIOCTL_TXEN;
- writel(reg_val, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
-
- /* enable DMA DRQ mode for play */
- reg_val = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOINT);
- reg_val |= SUNXI_HDMIAUDIOINT_TXDRQEN;
- writel(reg_val, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOINT);
-
- //Global Enable Digital Audio Interface
- reg_val = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
- reg_val |= SUNXI_HDMIAUDIOCTL_GEN;
- writel(reg_val, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
- }else{
- /* HDMIAUDIO TX DISABLE */
- reg_val = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
- reg_val &= ~SUNXI_HDMIAUDIOCTL_TXEN;
- writel(reg_val, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
-
- /* DISBALE dma DRQ mode */
- reg_val = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOINT);
- reg_val &= ~SUNXI_HDMIAUDIOINT_TXDRQEN;
- writel(reg_val, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOINT);
-
- //Global disable Digital Audio Interface
- reg_val = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
- reg_val &= ~SUNXI_HDMIAUDIOCTL_GEN;
- writel(reg_val, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
- }
}
static int sunxi_hdmiaudio_set_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
{
- u32 reg_val;
- u32 reg_val1;
-
- if (sunxi_is_sun7i())
- return 0; /* No rx / tx control, etc. on sun7i() */
-
- //SDO ON
- reg_val = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
- reg_val |= (SUNXI_HDMIAUDIOCTL_SDO0EN | SUNXI_HDMIAUDIOCTL_SDO1EN |
SUNXI_HDMIAUDIOCTL_SDO2EN | SUNXI_HDMIAUDIOCTL_SDO3EN);
- writel(reg_val, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
-
- /* master or slave selection */
- reg_val = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
- switch(fmt & SND_SOC_DAIFMT_MASTER_MASK) {
- case SND_SOC_DAIFMT_CBM_CFM: /* codec clk & frm master */
- reg_val |= SUNXI_HDMIAUDIOCTL_MS;
- break;
- case SND_SOC_DAIFMT_CBS_CFS: /* codec clk & frm slave */
- reg_val &= ~SUNXI_HDMIAUDIOCTL_MS;
- break;
- default:
- return -EINVAL;
- }
- writel(reg_val, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
-
- /* pcm or hdmiaudio mode selection */
- reg_val = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
- reg_val1 = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOFAT0);
- reg_val1 &= ~SUNXI_HDMIAUDIOFAT0_FMT_RVD;
- switch(fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
- case SND_SOC_DAIFMT_I2S: /* I2S mode */
- reg_val &= ~SUNXI_HDMIAUDIOCTL_PCM;
- reg_val1 |= SUNXI_HDMIAUDIOFAT0_FMT_I2S;
- break;
- case SND_SOC_DAIFMT_RIGHT_J: /* Right Justified mode */
- reg_val &= ~SUNXI_HDMIAUDIOCTL_PCM;
- reg_val1 |= SUNXI_HDMIAUDIOFAT0_FMT_RGT;
- break;
- case SND_SOC_DAIFMT_LEFT_J: /* Left Justified mode */
- reg_val &= ~SUNXI_HDMIAUDIOCTL_PCM;
- reg_val1 |= SUNXI_HDMIAUDIOFAT0_FMT_LFT;
- break;
- case SND_SOC_DAIFMT_DSP_A: /* L data msb after FRM LRC */
- reg_val |= SUNXI_HDMIAUDIOCTL_PCM;
- reg_val1 &= ~SUNXI_HDMIAUDIOFAT0_LRCP;
- break;
- case SND_SOC_DAIFMT_DSP_B: /* L data msb during FRM LRC */
- reg_val |= SUNXI_HDMIAUDIOCTL_PCM;
- reg_val1 |= SUNXI_HDMIAUDIOFAT0_LRCP;
- break;
- default:
- return -EINVAL;
- }
- writel(reg_val, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
- writel(reg_val1, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOFAT0);
-
- /* DAI signal inversions */
- reg_val1 = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOFAT0);
- switch(fmt & SND_SOC_DAIFMT_INV_MASK) {
- case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */
- reg_val1 &= ~SUNXI_HDMIAUDIOFAT0_LRCP;
- reg_val1 &= ~SUNXI_HDMIAUDIOFAT0_BCP;
- break;
- case SND_SOC_DAIFMT_NB_IF: /* normal bclk + inv frm */
- reg_val1 |= SUNXI_HDMIAUDIOFAT0_LRCP;
- reg_val1 &= ~SUNXI_HDMIAUDIOFAT0_BCP;
- break;
- case SND_SOC_DAIFMT_IB_NF: /* invert bclk + nor frm */
- reg_val1 &= ~SUNXI_HDMIAUDIOFAT0_LRCP;
- reg_val1 |= SUNXI_HDMIAUDIOFAT0_BCP;
- break;
- case SND_SOC_DAIFMT_IB_IF: /* invert bclk + frm */
- reg_val1 |= SUNXI_HDMIAUDIOFAT0_LRCP;
- reg_val1 |= SUNXI_HDMIAUDIOFAT0_BCP;
- break;
- }
- writel(reg_val1, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOFAT0);
-
- /* word select size */
- reg_val = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOFAT0);
- reg_val &= ~SUNXI_HDMIAUDIOFAT0_WSS_32BCLK;
- if(sunxi_hdmiaudio.ws_size == 16)
- reg_val |= SUNXI_HDMIAUDIOFAT0_WSS_16BCLK;
- else if(sunxi_hdmiaudio.ws_size == 20)
- reg_val |= SUNXI_HDMIAUDIOFAT0_WSS_20BCLK;
- else if(sunxi_hdmiaudio.ws_size == 24)
- reg_val |= SUNXI_HDMIAUDIOFAT0_WSS_24BCLK;
- else
- reg_val |= SUNXI_HDMIAUDIOFAT0_WSS_32BCLK;
- writel(reg_val, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOFAT0);
-
- /* PCM REGISTER setup */
- reg_val = sunxi_hdmiaudio.pcm_txtype&0x3;
- reg_val |= sunxi_hdmiaudio.pcm_rxtype<<2;
-
- if(!sunxi_hdmiaudio.pcm_sync_type)
- reg_val |= SUNXI_HDMIAUDIOFAT1_SSYNC;
//short sync
- if(sunxi_hdmiaudio.pcm_sw == 16)
- reg_val |= SUNXI_HDMIAUDIOFAT1_SW;
-
- reg_val |=((sunxi_hdmiaudio.pcm_start_slot - 1)&0x3)<<6;
//start slot index
-
- reg_val |= sunxi_hdmiaudio.pcm_lsb_first<<9; //MSB
or LSB first
-
- if(sunxi_hdmiaudio.pcm_sync_period == 256)
- reg_val |= 0x4<<12;
- else if (sunxi_hdmiaudio.pcm_sync_period == 128)
- reg_val |= 0x3<<12;
- else if (sunxi_hdmiaudio.pcm_sync_period == 64)
- reg_val |= 0x2<<12;
- else if (sunxi_hdmiaudio.pcm_sync_period == 32)
- reg_val |= 0x1<<12;
- writel(reg_val, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOFAT1);
-
- /* set FIFO control register */
- reg_val = 0 & 0x3;
- reg_val |= (0 & 0x1)<<2;
- reg_val |= SUNXI_HDMIAUDIOFCTL_RXTL(0xf);
//RX FIFO trigger level
- reg_val |= SUNXI_HDMIAUDIOFCTL_TXTL(0x40);
//TX FIFO empty trigger level
- writel(reg_val, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOFCTL);
return 0;
}
@@ -316,72 +105,11 @@ static int sunxi_hdmiaudio_trigger(struct
snd_pcm_substream *substream,
static int sunxi_hdmiaudio_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
unsigned int freq, int dir)
{
- if (sunxi_is_sun7i())
- return 0; /* No rx / tx control, etc. on sun7i() */
-
- if (!freq) {
- clk_set_rate(hdmiaudio_pll2clk, 24576000);
- } else {
- clk_set_rate(hdmiaudio_pll2clk, 22579200);
- }
-
return 0;
}
static int sunxi_hdmiaudio_set_clkdiv(struct snd_soc_dai *cpu_dai, int div_id,
int div)
{
- u32 reg;
-
- if (sunxi_is_sun7i())
- return 0; /* No rx / tx control, etc. on sun7i() */
-
- switch (div_id) {
- case SUNXI_DIV_MCLK:
- if(div <= 8)
- div = (div >>1);
- else if(div == 12)
- div = 0x5;
- else if(div == 16)
- div = 0x6;
- else if(div == 24)
- div = 0x7;
- else if(div == 32)
- div = 0x8;
- else if(div == 48)
- div = 0x9;
- else if(div == 64)
- div = 0xa;
- reg = (readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCLKD) &
~SUNXI_HDMIAUDIOCLKD_MCLK_MASK) | (div << SUNXI_HDMIAUDIOCLKD_MCLK_OFFS);
- writel(reg, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCLKD);
- break;
- case SUNXI_DIV_BCLK:
- if(div <= 8)
- div = (div>>1) - 1;
- else if(div == 12)
- div = 0x4;
- else if(div == 16)
- div = 0x5;
- else if(div == 32)
- div = 0x6;
- else if(div == 64)
- div = 0x7;
- reg = (readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCLKD) &
~SUNXI_HDMIAUDIOCLKD_BCLK_MASK) | (div <<SUNXI_HDMIAUDIOCLKD_BCLK_OFFS);
- writel(reg, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCLKD);
- break;
- default:
- return -EINVAL;
- }
-
- //diable MCLK output when high samplerate
- reg = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCLKD);
- if(!(reg & 0xF)) {
- reg &= ~SUNXI_HDMIAUDIOCLKD_MCLKOEN;
- writel(reg, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCLKD);
- } else {
- reg |= SUNXI_HDMIAUDIOCLKD_MCLKOEN;
- writel(reg, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCLKD);
- }
-
return 0;
}
@@ -400,82 +128,34 @@ static int sunxi_hdmiaudio_dai_remove(struct snd_soc_dai
*dai)
return 0;
}
-static void hdmiaudioregsave(void)
-{
- regsave[0] = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
- regsave[1] = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOFAT0);
- regsave[2] = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOFAT1);
- regsave[3] = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOFCTL) |
(0x3<<24);
- regsave[4] = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOINT);
- regsave[5] = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCLKD);
- regsave[6] = readl(sunxi_hdmiaudio.regs + SUNXI_TXCHSEL);
- regsave[7] = readl(sunxi_hdmiaudio.regs + SUNXI_TXCHMAP);
-}
-
-static void hdmiaudioregrestore(void)
-{
- writel(regsave[0], sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
- writel(regsave[1], sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOFAT0);
- writel(regsave[2], sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOFAT1);
- writel(regsave[3], sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOFCTL);
- writel(regsave[4], sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOINT);
- writel(regsave[5], sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCLKD);
- writel(regsave[6], sunxi_hdmiaudio.regs + SUNXI_TXCHSEL);
- writel(regsave[7], sunxi_hdmiaudio.regs + SUNXI_TXCHMAP);
-}
-
static int sunxi_hdmiaudio_suspend(struct snd_soc_dai *cpu_dai)
{
- u32 reg_val;
-
- if (sunxi_is_sun7i())
- return 0; /* No rx / tx control, etc. on sun7i() */
-
- printk("[HDMIAUDIO]Entered %s\n", __func__);
-
- //Global Enable Digital Audio Interface
- reg_val = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
- reg_val &= ~SUNXI_HDMIAUDIOCTL_GEN;
- writel(reg_val, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
-
- hdmiaudioregsave();
- //release the module clock
- clk_disable(hdmiaudio_moduleclk);
-
- clk_disable(hdmiaudio_apbclk);
+ printk("[HDMIAUDIO]Entered %s\n", __func__);
- //printk("[HDMIAUDIO]PLL2 0x01c20008 = %#x, line = %d\n", *(volatile
int*)0xF1C20008, __LINE__);
- printk("[HDMIAUDIO]SPECIAL CLK 0x01c20068 = %#x, line= %d\n",
*(volatile int*)0xF1C20068, __LINE__);
- printk("[HDMIAUDIO]SPECIAL CLK 0x01c200B8 = %#x, line = %d\n",
*(volatile int*)0xF1C200B8, __LINE__);
+ /*
+ * printk("[HDMIAUDIO]PLL2 0x01c20008 = %#x, line = %d\n",
+ * *(volatile int *)0xF1C20008, __LINE__);
+ */
+ printk("[HDMIAUDIO]SPECIAL CLK 0x01c20068 = %#x, line= %d\n",
+ *(volatile int *)0xF1C20068, __LINE__);
+ printk("[HDMIAUDIO]SPECIAL CLK 0x01c200B8 = %#x, line = %d\n",
+ *(volatile int *)0xF1C200B8, __LINE__);
return 0;
}
static int sunxi_hdmiaudio_resume(struct snd_soc_dai *cpu_dai)
{
- u32 reg_val;
-
- if (sunxi_is_sun7i())
- return 0; /* No rx / tx control, etc. on sun7i() */
-
printk("[HDMIAUDIO]Entered %s\n", __func__);
- //release the module clock
- clk_enable(hdmiaudio_apbclk);
-
- //release the module clock
- clk_enable(hdmiaudio_moduleclk);
-
- hdmiaudioregrestore();
-
- //Global Enable Digital Audio Interface
- reg_val = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
- reg_val |= SUNXI_HDMIAUDIOCTL_GEN;
- writel(reg_val, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
-
- //printk("[HDMIAUDIO]PLL2 0x01c20008 = %#x, line = %d\n", *(volatile
int*)0xF1C20008, __LINE__);
- printk("[HDMIAUDIO]SPECIAL CLK 0x01c20068 = %#x, line= %d\n",
*(volatile int*)0xF1C20068, __LINE__);
- printk("[HDMIAUDIO]SPECIAL CLK 0x01c200B8 = %#x, line = %d\n",
*(volatile int*)0xF1C200B8, __LINE__);
+ /*
+ * printk("[HDMIAUDIO]PLL2 0x01c20008 = %#x, line = %d\n",
+ * *(volatile int *)0xF1C20008, __LINE__);
+ */
+ printk("[HDMIAUDIO]SPECIAL CLK 0x01c20068 = %#x, line= %d\n",
+ *(volatile int *)0xF1C20068, __LINE__);
+ printk("[HDMIAUDIO]SPECIAL CLK 0x01c200B8 = %#x, line = %d\n",
+ *(volatile int *)0xF1C200B8, __LINE__);
return 0;
}
@@ -505,85 +185,11 @@ static struct snd_soc_dai_driver sunxi_hdmiaudio_dai = {
static int __devinit sunxi_hdmiaudio_dev_probe(struct platform_device *pdev)
{
- int reg_val = 0;
- int ret = 0;
-
- if (sunxi_is_sun7i()) {
- /* No rx / tx control, etc. on sun7i() */
- return snd_soc_register_dai(&pdev->dev, &sunxi_hdmiaudio_dai);
- }
-
- sunxi_hdmiaudio.regs = ioremap(SUNXI_HDMIAUDIOBASE, 0x100);
- if (sunxi_hdmiaudio.regs == NULL)
- return -ENXIO;
-
- sunxi_hdmiaudio.ccmregs = ioremap(SUNXI_CCMBASE, 0x100);
- if (sunxi_hdmiaudio.ccmregs == NULL)
- return -ENXIO;
-
- sunxi_hdmiaudio.ioregs = ioremap(0x01C20800, 0x100);
- if (sunxi_hdmiaudio.ioregs == NULL)
- return -ENXIO;
-
- //hdmiaudio apbclk
- hdmiaudio_apbclk = clk_get(NULL, "apb_i2s");
- if(-1 == clk_enable(hdmiaudio_apbclk)){
- printk("hdmiaudio_apbclk failed! line = %d\n", __LINE__);
- }
-
- hdmiaudio_pllx8 = clk_get(NULL, "audio_pllx8");
-
- //hdmiaudio pll2clk
- hdmiaudio_pll2clk = clk_get(NULL, "audio_pll");
-
- //hdmiaudio module clk
- hdmiaudio_moduleclk = clk_get(NULL, "i2s");
-
- if(clk_set_parent(hdmiaudio_moduleclk, hdmiaudio_pll2clk)){
- printk("try to set parent of hdmiaudio_moduleclk to
hdmiaudio_pll2ck failed! line = %d\n",__LINE__);
- }
-
-
- if(clk_set_rate(hdmiaudio_moduleclk, 24576000/8)){
- printk("set hdmiaudio_moduleclk clock freq to 24576000 failed!
line = %d\n", __LINE__);
- }
-
-
- if(-1 == clk_enable(hdmiaudio_moduleclk)){
- printk("open hdmiaudio_moduleclk failed! line = %d\n",
__LINE__);
- }
-
- reg_val = readl(sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
- reg_val |= SUNXI_HDMIAUDIOCTL_GEN;
- writel(reg_val, sunxi_hdmiaudio.regs + SUNXI_HDMIAUDIOCTL);
-
- ret = snd_soc_register_dai(&pdev->dev, &sunxi_hdmiaudio_dai);
-
- iounmap(sunxi_hdmiaudio.ioregs);
-
- return 0;
+ return snd_soc_register_dai(&pdev->dev, &sunxi_hdmiaudio_dai);
}
static int __devexit sunxi_hdmiaudio_dev_remove(struct platform_device *pdev)
{
- if (sunxi_is_sun7i()) {
- /* No rx / tx control, etc. on sun7i() */
- snd_soc_unregister_dai(&pdev->dev);
- return 0;
- }
-
- //release the module clock
- clk_disable(hdmiaudio_moduleclk);
-
- //release pllx8clk
- clk_put(hdmiaudio_pllx8);
-
- //release pll2clk
- clk_put(hdmiaudio_pll2clk);
-
- //release apbclk
- clk_put(hdmiaudio_apbclk);
-
snd_soc_unregister_dai(&pdev->dev);
platform_set_drvdata(pdev, NULL);
return 0;
diff --git a/sound/soc/sunxi/hdmiaudio/sunxi-hdmiaudio.h
b/sound/soc/sunxi/hdmiaudio/sunxi-hdmiaudio.h
deleted file mode 100644
index 9f4a0cc..0000000
--- a/sound/soc/sunxi/hdmiaudio/sunxi-hdmiaudio.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * sound\soc\sunxi\hdmiaudio\sunxi-hdmiaudio.h
- * (C) Copyright 2007-2011
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * chenpailin <chenpai...@allwinnertech.com>
- *
- * some simple description for this code
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- */
-#ifndef SUNXI_HDMIAUIDO_H_
-#define SUNXI_HDMIAUIDO_H_
-#include <linux/drv_hdmi.h>
-
-/*------------------------------------------------------------*/
-/* REGISTER definition */
-
-/* HDMIAUDIO REGISTER */
-#define SUNXI_HDMIAUDIOBASE (0x01C22400)
-
-#define SUNXI_HDMIAUDIOCTL (0x00)
- #define SUNXI_HDMIAUDIOCTL_SDO3EN (1<<11)
- #define SUNXI_HDMIAUDIOCTL_SDO2EN (1<<10)
- #define SUNXI_HDMIAUDIOCTL_SDO1EN (1<<9)
- #define SUNXI_HDMIAUDIOCTL_SDO0EN (1<<8)
- #define SUNXI_HDMIAUDIOCTL_ASS (1<<6)
- #define SUNXI_HDMIAUDIOCTL_MS (1<<5)
- #define SUNXI_HDMIAUDIOCTL_PCM (1<<4)
- #define SUNXI_HDMIAUDIOCTL_LOOP (1<<3)
- #define SUNXI_HDMIAUDIOCTL_TXEN (1<<2)
- #define SUNXI_HDMIAUDIOCTL_RXEN (1<<1)
- #define SUNXI_HDMIAUDIOCTL_GEN (1<<0)
-
-#define SUNXI_HDMIAUDIOFAT0 (0x04)
- #define SUNXI_HDMIAUDIOFAT0_LRCP
(1<<7)
- #define SUNXI_HDMIAUDIOFAT0_BCP (1<<6)
- #define SUNXI_HDMIAUDIOFAT0_SR_RVD (3<<4)
- #define SUNXI_HDMIAUDIOFAT0_SR_16BIT (0<<4)
- #define SUNXI_HDMIAUDIOFAT0_SR_20BIT (1<<4)
- #define SUNXI_HDMIAUDIOFAT0_SR_24BIT (2<<4)
- #define SUNXI_HDMIAUDIOFAT0_WSS_16BCLK (0<<2)
- #define SUNXI_HDMIAUDIOFAT0_WSS_20BCLK (1<<2)
- #define SUNXI_HDMIAUDIOFAT0_WSS_24BCLK (2<<2)
- #define SUNXI_HDMIAUDIOFAT0_WSS_32BCLK (3<<2)
- #define SUNXI_HDMIAUDIOFAT0_FMT_I2S (0<<0)
- #define SUNXI_HDMIAUDIOFAT0_FMT_LFT (1<<0)
- #define SUNXI_HDMIAUDIOFAT0_FMT_RGT (2<<0)
- #define SUNXI_HDMIAUDIOFAT0_FMT_RVD (3<<0)
-
-#define SUNXI_HDMIAUDIOFAT1 (0x08)
- #define SUNXI_HDMIAUDIOFAT1_SYNCLEN_16BCLK (0<<12)
- #define SUNXI_HDMIAUDIOFAT1_SYNCLEN_32BCLK (1<<12)
- #define SUNXI_HDMIAUDIOFAT1_SYNCLEN_64BCLK (2<<12)
- #define SUNXI_HDMIAUDIOFAT1_SYNCLEN_128BCLK (3<<12)
- #define SUNXI_HDMIAUDIOFAT1_SYNCLEN_256BCLK (4<<12)
- #define SUNXI_HDMIAUDIOFAT1_SYNCOUTEN (1<<11)
- #define SUNXI_HDMIAUDIOFAT1_OUTMUTE (1<<10)
- #define SUNXI_HDMIAUDIOFAT1_MLS (1<<9)
- #define SUNXI_HDMIAUDIOFAT1_SEXT
(1<<8)
- #define SUNXI_HDMIAUDIOFAT1_SI_1ST (0<<6)
- #define SUNXI_HDMIAUDIOFAT1_SI_2ND (1<<6)
- #define SUNXI_HDMIAUDIOFAT1_SI_3RD (2<<6)
- #define SUNXI_HDMIAUDIOFAT1_SI_4TH (3<<6)
- #define SUNXI_HDMIAUDIOFAT1_SW (1<<5)
- #define SUNXI_HDMIAUDIOFAT1_SSYNC (1<<4)
- #define SUNXI_HDMIAUDIOFAT1_RXPDM_16PCM (0<<2)
- #define SUNXI_HDMIAUDIOFAT1_RXPDM_8PCM (1<<2)
- #define SUNXI_HDMIAUDIOFAT1_RXPDM_8ULAW (2<<2)
- #define SUNXI_HDMIAUDIOFAT1_RXPDM_8ALAW (3<<2)
- #define SUNXI_HDMIAUDIOFAT1_TXPDM_16PCM (0<<0)
- #define SUNXI_HDMIAUDIOFAT1_TXPDM_8PCM (1<<0)
- #define SUNXI_HDMIAUDIOFAT1_TXPDM_8ULAW (2<<0)
- #define SUNXI_HDMIAUDIOFAT1_TXPDM_8ALAW (3<<0)
-
-#define SUNXI_HDMIAUDIOTXFIFO (0x0C)
-
-#define SUNXI_HDMIAUDIORXFIFO (0x10)
-
-#define SUNXI_HDMIAUDIOFCTL (0x14)
- #define SUNXI_HDMIAUDIOFCTL_FIFOSRC (1<<31)
- #define SUNXI_HDMIAUDIOFCTL_FTX (1<<25)
- #define SUNXI_HDMIAUDIOFCTL_FRX (1<<24)
- #define SUNXI_HDMIAUDIOFCTL_TXTL(v) ((v)<<12)
- #define SUNXI_HDMIAUDIOFCTL_RXTL(v) ((v)<<4)
- #define SUNXI_HDMIAUDIOFCTL_TXIM_MOD0 (0<<2)
- #define SUNXI_HDMIAUDIOFCTL_TXIM_MOD1 (1<<2)
- #define SUNXI_HDMIAUDIOFCTL_RXOM_MOD0 (0<<0)
- #define SUNXI_HDMIAUDIOFCTL_RXOM_MOD1 (1<<0)
- #define SUNXI_HDMIAUDIOFCTL_RXOM_MOD2 (2<<0)
- #define SUNXI_HDMIAUDIOFCTL_RXOM_MOD3 (3<<0)
-
-#define SUNXI_HDMIAUDIOFSTA (0x18)
- #define SUNXI_HDMIAUDIOFSTA_TXE (1<<28)
- #define SUNXI_HDMIAUDIOFSTA_TXECNT(v) ((v)<<16)
- #define SUNXI_HDMIAUDIOFSTA_RXA (1<<8)
- #define SUNXI_HDMIAUDIOFSTA_RXACNT(v) ((v)<<0)
-
-#define SUNXI_HDMIAUDIOINT (0x1C)
- #define SUNXI_HDMIAUDIOINT_TXDRQEN (1<<7)
- #define SUNXI_HDMIAUDIOINT_TXUIEN (1<<6)
- #define SUNXI_HDMIAUDIOINT_TXOIEN (1<<5)
- #define SUNXI_HDMIAUDIOINT_TXEIEN (1<<4)
- #define SUNXI_HDMIAUDIOINT_RXDRQEN (1<<2)
- #define SUNXI_HDMIAUDIOINT_RXOIEN (1<<1)
- #define SUNXI_HDMIAUDIOINT_RXAIEN (1<<0)
-
-#define SUNXI_HDMIAUDIOISTA (0x20)
- #define SUNXI_HDMIAUDIOISTA_TXUISTA (1<<6)
- #define SUNXI_HDMIAUDIOISTA_TXOISTA (1<<5)
- #define SUNXI_HDMIAUDIOISTA_TXEISTA (1<<4)
- #define SUNXI_HDMIAUDIOISTA_RXOISTA (1<<1)
- #define SUNXI_HDMIAUDIOISTA_RXAISTA (1<<0)
-
-#define SUNXI_HDMIAUDIOCLKD (0x24)
- #define SUNXI_HDMIAUDIOCLKD_MCLKOEN (1<<7)
- #define SUNXI_HDMIAUDIOCLKD_BCLKDIV_2 (0<<4)
- #define SUNXI_HDMIAUDIOCLKD_BCLKDIV_4 (1<<4)
- #define SUNXI_HDMIAUDIOCLKD_BCLKDIV_6 (2<<4)
- #define SUNXI_HDMIAUDIOCLKD_BCLKDIV_8 (3<<4)
- #define SUNXI_HDMIAUDIOCLKD_BCLKDIV_12 (4<<4)
- #define SUNXI_HDMIAUDIOCLKD_BCLKDIV_16 (5<<4)
- #define SUNXI_HDMIAUDIOCLKD_BCLKDIV_32 (6<<4)
- #define SUNXI_HDMIAUDIOCLKD_BCLKDIV_64 (7<<4)
- #define SUNXI_HDMIAUDIOCLKD_MCLKDIV_1 (0<<0)
- #define SUNXI_HDMIAUDIOCLKD_MCLKDIV_2 (1<<0)
- #define SUNXI_HDMIAUDIOCLKD_MCLKDIV_4 (2<<0)
- #define SUNXI_HDMIAUDIOCLKD_MCLKDIV_6 (3<<0)
- #define SUNXI_HDMIAUDIOCLKD_MCLKDIV_8 (4<<0)
- #define SUNXI_HDMIAUDIOCLKD_MCLKDIV_12 (5<<0)
- #define SUNXI_HDMIAUDIOCLKD_MCLKDIV_16 (6<<0)
- #define SUNXI_HDMIAUDIOCLKD_MCLKDIV_24 (7<<0)
- #define SUNXI_HDMIAUDIOCLKD_MCLKDIV_32 (8<<0)
- #define SUNXI_HDMIAUDIOCLKD_MCLKDIV_48 (9<<0)
- #define SUNXI_HDMIAUDIOCLKD_MCLKDIV_64 (10<<0)
-
-#define SUNXI_HDMIAUDIOTXCNT (0x28)
-
-#define SUNXI_HDMIAUDIORXCNT (0x2C)
-
-#define SUNXI_TXCHSEL (0x30)
- #define SUNXI_TXCHSEL_CHNUM(v) (((v)-1)<<0)
-
-#define SUNXI_TXCHMAP (0x34)
- #define SUNXI_TXCHMAP_CH7(v) (((v)-1)<<28)
- #define SUNXI_TXCHMAP_CH6(v) (((v)-1)<<24)
- #define SUNXI_TXCHMAP_CH5(v) (((v)-1)<<20)
- #define SUNXI_TXCHMAP_CH4(v) (((v)-1)<<16)
- #define SUNXI_TXCHMAP_CH3(v) (((v)-1)<<12)
- #define SUNXI_TXCHMAP_CH2(v) (((v)-1)<<8)
- #define SUNXI_TXCHMAP_CH1(v) (((v)-1)<<4)
- #define SUNXI_TXCHMAP_CH0(v) (((v)-1)<<0)
-
-#define SUNXI_RXCHSEL (0x38)
- #define SUNXI_RXCHSEL_CHNUM(v) (((v)-1)<<0)
-
-#define SUNXI_RXCHMAP (0x3C)
- #define SUNXI_RXCHMAP_CH3(v) (((v)-1)<<12)
- #define SUNXI_RXCHMAP_CH2(v) (((v)-1)<<8)
- #define SUNXI_RXCHMAP_CH1(v) (((v)-1)<<4)
- #define SUNXI_RXCHMAP_CH0(v) (((v)-1)<<0)
-
-
-/* DMA REGISTER */
-#define SUNXI_DMABASE (0x01C02000)
-
-#define SUNXI_DMAIRQEN (0x0)
- #define SUNXI_DMAIRQEN_NDMA_FULLEN(v)
(1<<((v)*2+1))
- #define SUNXI_DMAIRQEN_NDMA_HALFEN(v)
(1<<((v)*2))
-
-#define SUNXI_DMAIRQPENDING (0x4)
- #define SUNXI_DMAIRQPENGDING_NDMA_FULLPEND(v) (1<<((v)*2+1))
- #define SUNXI_DMAIRQPENGDING_NDMA_HALFPEND(v) (1<<((v)*2))
-
-#define SUNXI_NDMACFG(v) ((v)*0x20+0x100)
- #define SUNXI_NDMACFG_DMALOAD (1<<31)
- #define SUNXI_NDMACFG_BUSY
(1<<30)
- #define SUNXI_NDMACFG_CONTINUOUS (1<<29)
- #define SUNXI_NDMACFG_WAIT(v)
(((v)-1)<<26) //wait clock = 2^n example: 8 clocks = 2^3
- #define SUNXI_NDMACFG_DSTDATAWIDTH_8BIT (0<<24)
- #define SUNXI_NDMACFG_DSTDATAWIDTH_16BIT (1<<24)
- #define SUNXI_NDMACFG_DSTDATAWIDTH_32BIT (2<<24)
- #define SUNXI_NDMACFG_DSTDATAWIDTH_RVD (3<<24)
- #define SUNXI_NDMACFG_DSTBURST4 (1<<23)
- #define SUNXI_NDMACFG_DSTADDRTYPE_INC (0<<21)
- #define SUNXI_NDMACFG_DSTADDRTYPE_CON (1<<21)
- #define SUNXI_NDMACFG_DSTTYPE_IRTX
(0x0<<16)
- #define SUNXI_NDMACFG_DSTTYPE_SPDIFTX (0x1<<16)
- #define SUNXI_NDMACFG_DSTTYPE_IISTX (0x2<<16)
- #define SUNXI_NDMACFG_DSTTYPE_AC97TX (0x3<<16)
- #define SUNXI_NDMACFG_DSTTYPE_SPI0TX (0x4<<16)
- #define SUNXI_NDMACFG_DSTTYPE_SPI1TX (0x5<<16)
- #define SUNXI_NDMACFG_DSTTYPE_SPI2TX (0x6<<16)
- #define SUNXI_NDMACFG_DSTTYPE_UART0TX (0x8<<16)
- #define SUNXI_NDMACFG_DSTTYPE_UART1TX (0x9<<16)
- #define SUNXI_NDMACFG_DSTTYPE_UART2TX (0xA<<16)
- #define SUNXI_NDMACFG_DSTTYPE_UART3TX (0xB<<16)
- #define SUNXI_NDMACFG_DSTTYPE_AUDIODA (0xC<<16)
- #define SUNXI_NDMACFG_DSTTYPE_NFC
(0xF<<16)
- #define SUNXI_NDMACFG_DSTTYPE_SRAM
(0x10<<16)
- #define SUNXI_NDMACFG_DSTTYPE_DRAM
(0x11<<16)
- #define SUNXI_NDMACFG_DSTTYPE_UART4TX (0x12<<16)
- #define SUNXI_NDMACFG_DSTTYPE_UART5TX (0x13<<16)
- #define SUNXI_NDMACFG_DSTTYPE_UART6TX (0x14<<16)
- #define SUNXI_NDMACFG_DSTTYPE_UART7TX (0x15<<16)
- #define SUNXI_NDMACFG_SRCDATAWIDTH_8BIT (0<<8)
- #define SUNXI_NDMACFG_SRCDATAWIDTH_16BIT (1<<8)
- #define SUNXI_NDMACFG_SRCDATAWIDTH_32BIT (2<<8)
- #define SUNXI_NDMACFG_SRCDATAWIDTH_RVD (3<<8)
- #define SUNXI_NDMACFG_SRCBURST4 (1<<7)
- #define SUNXI_NDMACFG_SRCADDRTYPE_INC (0<<5)
- #define SUNXI_NDMACFG_SRCADDRTYPE_CON (1<<5)
- #define SUNXI_NDMACFG_SRCTYPE_IRRX (0x0<<0)
- #define SUNXI_NDMACFG_SRCTYPE_SPDIFRX (0x1<<0)
- #define SUNXI_NDMACFG_SRCTYPE_IISRX (0x2<<0)
- #define SUNXI_NDMACFG_SRCTYPE_AC97RX (0x3<<0)
- #define SUNXI_NDMACFG_SRCTYPE_SPI0RX (0x4<<0)
- #define SUNXI_NDMACFG_SRCTYPE_SPI1RX (0x5<<0)
- #define SUNXI_NDMACFG_SRCTYPE_SPI2RX (0x6<<0)
- #define SUNXI_NDMACFG_SRCTYPE_UART0RX (0x8<<0)
- #define SUNXI_NDMACFG_SRCTYPE_UART1RX (0x9<<0)
- #define SUNXI_NDMACFG_SRCTYPE_UART2RX (0xA<<0)
- #define SUNXI_NDMACFG_SRCTYPE_UART3RX (0xB<<0)
- #define SUNXI_NDMACFG_SRCTYPE_AUDIOAD (0xC<<0)
- #define SUNXI_NDMACFG_SRCTYPE_TPAD (0xD<<0)
- #define SUNXI_NDMACFG_SRCTYPE_NFC (0xF<<0)
- #define SUNXI_NDMACFG_SRCTYPE_SRAM
(0x10<<0)
- #define SUNXI_NDMACFG_SRCTYPE_DRAM
(0x11<<0)
- #define SUNXI_NDMACFG_SRCTYPE_UART4RX (0x12<<0)
- #define SUNXI_NDMACFG_SRCTYPE_UART5RX (0x13<<0)
- #define SUNXI_NDMACFG_SRCTYPE_UART6RX (0x14<<0)
- #define SUNXI_NDMACFG_SRCTYPE_UART7RX (0x15<<0)
-
-#define SUNXI_NDMASRCADDR(v) ((v)*0x20 + 0x100 + 4)
-
-#define SUNXI_NDMADSTADDR(v) ((v)*0x20 + 0x100 + 8)
-
-#define SUNXI_NDMACNT(v) ((v)*0x20 + 0x100 + 0xC)
-
-
-/* CCM REGISTER */
-#define SUNXI_CCMBASE (0x01C20000)
-
-#define SUNXI_CCM_AUDIO_HOSC_PLL_REG (0x08)
- #define SUNXI_CCM_AUDIO_HOSC_PLL_REG_AUDIOEN (1<<31)
- #define SUNXI_CCM_AUDIO_HOSC_PLL_REG_FRE225792MHZ (0<<27)
- #define SUNXI_CCM_AUDIO_HOSC_PLL_REG_FRE24576MHZ (1<<27)
-
-#define SUNXI_CCM_APB_GATE_REG (0x68)
- #define SUNXI_CCM_APB_GATE_REG_IISGATE (1<<3)
-
-#define SUNXI_CCM_AUDIO_CLK_REG (0xb8)
- #define SUNXI_CCM_AUDIO_CLK_REG_IISSPECIALGATE (1<<31)
- #define SUNXI_CCM_AUDIO_CLK_REG_DIV(v)
((v)<<16)
-/*------------------------------------------------------------*/
-
-/*------------------------------------------------------------*/
-/* Clock dividers */
-#define SUNXI_DIV_MCLK 0
-#define SUNXI_DIV_BCLK 1
-
-#define SUNXI_HDMIAUDIOCLKD_MCLK_MASK 0x0f
-#define SUNXI_HDMIAUDIOCLKD_MCLK_OFFS 0
-#define SUNXI_HDMIAUDIOCLKD_BCLK_MASK 0x070
-#define SUNXI_HDMIAUDIOCLKD_BCLK_OFFS 4
-#define SUNXI_HDMIAUDIOCLKD_MCLKEN_OFFS 7
-
-unsigned int sunxi_hdmiaudio_get_clockrate(void);
-extern struct sunxi_hdmiaudio_info sunxi_hdmiaudio;
-
-extern void sunxi_snd_txctrl_hdmiaudio(struct snd_pcm_substream *substream,
int on);
-extern void sunxi_snd_rxctrl_hdmiaudio(struct snd_pcm_substream *substream,
int on);
-
-struct sunxi_hdmiaudio_info {
- void __iomem *regs; /* IIS BASE */
- void __iomem *ccmregs; //CCM BASE
- void __iomem *ioregs; //IO BASE
-
- u32 slave; //0: master, 1: slave
- u32 mono; //0: stereo, 1: mono
- u32 samp_fs; //audio sample rate (unit in
kHz)
- u32 samp_res; //16 bits, 20 bits , 24 bits, 32 bits)
- u32 samp_format; //audio sample format (0: standard I2S,
1: left-justified, 2: right-justified, 3: pcm)
- u32 ws_size; //16 BCLK, 20 BCLK, 24 BCLK, 32
BCLK)
- u32 mclk_rate; //mclk frequency divide by fs (128fs,
192fs, 256fs, 384fs, 512fs, 768fs)
- u32 lrc_pol; //LRC clock polarity (0: normal
,1: inverted)
- u32 bclk_pol; //BCLK polarity (0: normal, 1: inverted)
- u32 pcm_txtype; //PCM transmitter type (0: 16-bits linear mode,
1: 8-bits linear mode, 2: u-law, 3: A-law)
- u32 pcm_rxtype; //PCM receiver type (0: 16-bits linear mode,
1: 8-bits linear mode, 2: u-law, 3: A-law)
- u32 pcm_sw; //PCM slot width (8: 8 bits,
16: 16 bits)
- u32 pcm_sync_period;//PCM sync period (16/32/64/128/256)
- u32 pcm_sync_type; //PCM sync symbol size (0: short sync, 1: long
sync)
- u32 pcm_start_slot;//PCM start slot index (1--4)
- u32 pcm_lsb_first; //0: MSB first, 1: LSB first
- u32 pcm_ch_num; //PCM channel number (1: one channel, 2: two
channel)
-
-};
-
-extern struct sunxi_hdmiaudio_info sunxi_hdmiaudio;
-#endif
diff --git a/sound/soc/sunxi/hdmiaudio/sunxi-hdmipcm.c
b/sound/soc/sunxi/hdmiaudio/sunxi-hdmipcm.c
index d8e3298..dc5704a 100644
--- a/sound/soc/sunxi/hdmiaudio/sunxi-hdmipcm.c
+++ b/sound/soc/sunxi/hdmiaudio/sunxi-hdmipcm.c
@@ -29,7 +29,6 @@
#include <mach/hardware.h>
#include <plat/dma_compat.h>
-#include "sunxi-hdmiaudio.h"
static volatile unsigned int dmasrc = 0;
static volatile unsigned int dmadst = 0;
diff --git a/sound/soc/sunxi/hdmiaudio/sunxi-sndhdmi.c
b/sound/soc/sunxi/hdmiaudio/sunxi-sndhdmi.c
index ee62f3c..953231e 100644
--- a/sound/soc/sunxi/hdmiaudio/sunxi-sndhdmi.c
+++ b/sound/soc/sunxi/hdmiaudio/sunxi-sndhdmi.c
@@ -24,8 +24,6 @@
#include <plat/sys_config.h>
#include <linux/io.h>
-#include "sunxi-hdmiaudio.h"
-
static int sunxi_sndhdmi_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
--
1.8.3.2
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