Hi Priit,
On 27 March 2017 at 04:20, Priit Laes wrote:
> +static struct ccu_nkmp pll_ve_clk = {
> + .enable = BIT(31),
> + .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
> + .k = _SUNXI_CCU_MULT(4, 2),
> + .m =
Hi Priit,
On 27 March 2017 at 04:20, Priit Laes wrote:
> Introduce a clock controller driver for sun4i A10 and sun7i A20
> series SoCs.
>
> Signed-off-by: Priit Laes
> ---
> drivers/clk/sunxi-ng/Kconfig | 13 +-
>
Introduce a clock controller driver for sun4i A10 and sun7i A20
series SoCs.
Signed-off-by: Priit Laes
---
drivers/clk/sunxi-ng/Kconfig | 13 +-
drivers/clk/sunxi-ng/Makefile |1 +-
drivers/clk/sunxi-ng/ccu-sunxi-a10-a20.c | 1532