The sunxi_emac driver is very specific to the IP used in the sun4i.
Thus rename it to what it actually is, the MAC driver for the sun4i MAC.
The rename also changes the variable and function names inside the
driver. There are no code changes in this patch however.
While here, use the BIT() macro for bitfields as well.
Signed-off-by: Olliver Schinagl <oli...@schinagl.nl>
---
drivers/net/Makefile | 2 +-
drivers/net/{sunxi_emac.c => sun4i_mac.c} | 260 +++++++++++++++---------------
2 files changed, 133 insertions(+), 129 deletions(-)
rename drivers/net/{sunxi_emac.c => sun4i_mac.c} (60%)
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index c5dd52bee2..9834d67146 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_DNET) += dnet.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
-obj-$(CONFIG_SUN4I_EMAC) += sunxi_emac.o
+obj-$(CONFIG_SUN4I_EMAC) += sun4i_mac.o
obj-$(CONFIG_SUN8I_EMAC) += sun8i_emac.o
obj-$(CONFIG_ENC28J60) += enc28j60.o
obj-$(CONFIG_EP93XX) += ep93xx_eth.o
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sun4i_mac.c
similarity index 60%
rename from drivers/net/sunxi_emac.c
rename to drivers/net/sun4i_mac.c
index 0dc37de242..ea52bd8a17 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sun4i_mac.c
@@ -1,5 +1,5 @@
/*
- * sunxi_emac.c -- Allwinner A10 ethernet driver
+ * sun4i_mac.c -- Allwinner A10 ethernet driver
*
* (C) Copyright 2012, Stefan Roese <s...@denx.de>
*
@@ -9,6 +9,7 @@
#include <common.h>
#include <dm.h>
#include <linux/err.h>
+#include <linux/bitops.h>
#include <malloc.h>
#include <miiphy.h>
#include <net.h>
@@ -17,7 +18,7 @@
#include <asm/arch/gpio.h>
/* EMAC register */
-struct emac_regs {
+struct sun4i_mac_regs {
u32 ctl; /* 0x00 */
u32 tx_mode; /* 0x04 */
u32 tx_flow; /* 0x08 */
@@ -67,111 +68,114 @@ struct sunxi_sramc_regs {
};
/* 0: Disable 1: Aborted frame enable(default) */
-#define EMAC_TX_AB_M (0x1 << 0)
+#define SUN4I_MAC_TX_AB_M BIT(0)
/* 0: CPU 1: DMA(default) */
-#define EMAC_TX_TM (0x1 << 1)
+#define SUN4I_MAC_TX_TM BIT(1)
-#define EMAC_TX_SETUP (0)
+#define SUN4I_MAC_TX_SETUP (0)
/* 0: DRQ asserted 1: DRQ automatically(default) */
-#define EMAC_RX_DRQ_MODE (0x1 << 1)
+#define SUN4I_MAC_RX_DRQ_MODE BIT(1)
/* 0: CPU 1: DMA(default) */
-#define EMAC_RX_TM (0x1 << 2)
+#define SUN4I_MAC_RX_TM BIT(2)
/* 0: Normal(default) 1: Pass all Frames */
-#define EMAC_RX_PA (0x1 << 4)
+#define SUN4I_MAC_RX_PA BIT(4)
/* 0: Normal(default) 1: Pass Control Frames */
-#define EMAC_RX_PCF (0x1 << 5)
+#define SUN4I_MAC_RX_PCF BIT(5)
/* 0: Normal(default) 1: Pass Frames with CRC Error */
-#define EMAC_RX_PCRCE (0x1 << 6)
+#define SUN4I_MAC_RX_PCRCE BIT(6)
/* 0: Normal(default) 1: Pass Frames with Length Error */
-#define EMAC_RX_PLE (0x1 << 7)
+#define SUN4I_MAC_RX_PLE BIT(7)
/* 0: Normal 1: Pass Frames length out of range(default) */
-#define EMAC_RX_POR (0x1 << 8)
+#define SUN4I_MAC_RX_POR BIT(8)
/* 0: Not accept 1: Accept unicast Packets(default) */
-#define EMAC_RX_UCAD (0x1 << 16)
+#define SUN4I_MAC_RX_UCAD BIT(16)
/* 0: Normal(default) 1: DA Filtering */
-#define EMAC_RX_DAF (0x1 << 17)
+#define SUN4I_MAC_RX_DAF BIT(17)
/* 0: Not accept 1: Accept multicast Packets(default) */
-#define EMAC_RX_MCO (0x1 << 20)
+#define SUN4I_MAC_RX_MCO BIT(20)
/* 0: Disable(default) 1: Enable Hash filter */
-#define EMAC_RX_MHF (0x1 << 21)
+#define SUN4I_MAC_RX_MHF BIT(21)
/* 0: Not accept 1: Accept Broadcast Packets(default) */
-#define EMAC_RX_BCO (0x1 << 22)
+#define SUN4I_MAC_RX_BCO BIT(22)
/* 0: Disable(default) 1: Enable SA Filtering */
-#define EMAC_RX_SAF (0x1 << 24)
+#define SUN4I_MAC_RX_SAF BIT(24)
/* 0: Normal(default) 1: Inverse Filtering */
-#define EMAC_RX_SAIF (0x1 << 25)
+#define SUN4I_MAC_RX_SAIF BIT(25)
-#define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
- EMAC_RX_MCO | EMAC_RX_BCO)
+#define SUN4I_MAC_RX_SETUP (SUN4I_MAC_RX_POR | SUN4I_MAC_RX_UCAD |
\
+ SUN4I_MAC_RX_DAF | SUN4I_MAC_RX_MCO | \
+ SUN4I_MAC_RX_BCO)
/* 0: Disable 1: Enable Receive Flow Control(default) */
-#define EMAC_MAC_CTL0_RFC (0x1 << 2)
+#define SUN4I_MAC_MAC_CTL0_RFC BIT(2)
/* 0: Disable 1: Enable Transmit Flow Control(default) */
-#define EMAC_MAC_CTL0_TFC (0x1 << 3)
+#define SUN4I_MAC_MAC_CTL0_TFC BIT(3)
-#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)
+#define SUN4I_MAC_MAC_CTL0_SETUP (SUN4I_MAC_MAC_CTL0_RFC | \
+ SUN4I_MAC_MAC_CTL0_TFC)
/* 0: Disable 1: Enable MAC Frame Length Checking(default) */
-#define EMAC_MAC_CTL1_FLC (0x1 << 1)
+#define SUN4I_MAC_MAC_CTL1_FLC BIT(1)
/* 0: Disable(default) 1: Enable Huge Frame */
-#define EMAC_MAC_CTL1_HF (0x1 << 2)
+#define SUN4I_MAC_MAC_CTL1_HF BIT(2)
/* 0: Disable(default) 1: Enable MAC Delayed CRC */
-#define EMAC_MAC_CTL1_DCRC (0x1 << 3)
+#define SUN4I_MAC_MAC_CTL1_DCRC BIT(3)
/* 0: Disable 1: Enable MAC CRC(default) */
-#define EMAC_MAC_CTL1_CRC (0x1 << 4)
+#define SUN4I_MAC_MAC_CTL1_CRC BIT(4)
/* 0: Disable 1: Enable MAC PAD Short frames(default) */
-#define EMAC_MAC_CTL1_PC (0x1 << 5)
+#define SUN4I_MAC_MAC_CTL1_PC BIT(5)
/* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */
-#define EMAC_MAC_CTL1_VC (0x1 << 6)
+#define SUN4I_MAC_MAC_CTL1_VC BIT(6)
/* 0: Disable(default) 1: Enable MAC auto detect Short frames */
-#define EMAC_MAC_CTL1_ADP (0x1 << 7)
+#define SUN4I_MAC_MAC_CTL1_ADP BIT(7)
/* 0: Disable(default) 1: Enable */
-#define EMAC_MAC_CTL1_PRE (0x1 << 8)
+#define SUN4I_MAC_MAC_CTL1_PRE BIT(8)
/* 0: Disable(default) 1: Enable */
-#define EMAC_MAC_CTL1_LPE (0x1 << 9)
+#define SUN4I_MAC_MAC_CTL1_LPE BIT(9)
/* 0: Disable(default) 1: Enable no back off */
-#define EMAC_MAC_CTL1_NB (0x1 << 12)
+#define SUN4I_MAC_MAC_CTL1_NB BIT(12)
/* 0: Disable(default) 1: Enable */
-#define EMAC_MAC_CTL1_BNB (0x1 << 13)
+#define SUN4I_MAC_MAC_CTL1_BNB BIT(13)
/* 0: Disable(default) 1: Enable */
-#define EMAC_MAC_CTL1_ED (0x1 << 14)
+#define SUN4I_MAC_MAC_CTL1_ED BIT(14)
-#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
- EMAC_MAC_CTL1_PC)
+#define SUN4I_MAC_MAC_CTL1_SETUP (SUN4I_MAC_MAC_CTL1_FLC | \
+ SUN4I_MAC_MAC_CTL1_CRC | \
+ SUN4I_MAC_MAC_CTL1_PC)
-#define EMAC_MAC_IPGT 0x15
+#define SUN4I_MAC_MAC_IPGT 0x15
-#define EMAC_MAC_NBTB_IPG1 0xc
-#define EMAC_MAC_NBTB_IPG2 0x12
+#define SUN4I_MAC_MAC_NBTB_IPG1 0xc
+#define SUN4I_MAC_MAC_NBTB_IPG2 0x12
-#define EMAC_MAC_CW 0x37
-#define EMAC_MAC_RM 0xf
+#define SUN4I_MAC_MAC_CW 0x37
+#define SUN4I_MAC_MAC_RM 0xf
-#define EMAC_MAC_MFL 0x0600
+#define SUN4I_MAC_MAC_MFL 0x0600
/* Receive status */
-#define EMAC_CRCERR (0x1 << 4)
-#define EMAC_LENERR (0x3 << 5)
+#define SUN4I_MAC_CRCERR BIT(4)
+#define SUN4I_MAC_LENERR (0x3 << 5)
-#define EMAC_RX_BUFSIZE 2000
+#define SUN4I_MAC_RX_BUFSIZE 2000
-struct emac_eth_dev {
- struct emac_regs *regs;
+struct sun4i_mac_eth_dev {
+ struct sun4i_mac_regs *regs;
struct mii_dev *bus;
struct phy_device *phydev;
int link_printed;
#ifdef CONFIG_DM_ETH
- uchar rx_buf[EMAC_RX_BUFSIZE];
+ uchar rx_buf[SUN4I_MAC_RX_BUFSIZE];
#endif
};
-struct emac_rxhdr {
+struct sun4i_mac_rxhdr {
s16 rx_len;
u16 rx_status;
};
-static void emac_inblk_32bit(void *reg, void *data, int count)
+static void sun4i_mac_inblk_32bit(void *reg, void *data, int count)
{
int cnt = (count + 3) >> 2;
@@ -185,7 +189,7 @@ static void emac_inblk_32bit(void *reg, void *data, int
count)
}
}
-static void emac_outblk_32bit(void *reg, void *data, int count)
+static void sun4i_mac_outblk_32bit(void *reg, void *data, int count)
{
int cnt = (count + 3) >> 2;
@@ -199,10 +203,10 @@ static void emac_outblk_32bit(void *reg, void *data, int
count)
}
/* Read a word from phyxcer */
-static int emac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+static int sun4i_mac_mdio_read(struct mii_dev *bus, int addr, int devad, int
reg)
{
- struct emac_eth_dev *priv = bus->priv;
- struct emac_regs *regs = priv->regs;
+ struct sun4i_mac_eth_dev *priv = bus->priv;
+ struct sun4i_mac_regs *regs = priv->regs;
/* issue the phy address and reg */
writel(addr << 8 | reg, ®s->mac_madr);
@@ -221,11 +225,11 @@ static int emac_mdio_read(struct mii_dev *bus, int addr,
int devad, int reg)
}
/* Write a word to phyxcer */
-static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+static int sun4i_mac_mdio_write(struct mii_dev *bus, int addr, int devad, int
reg,
u16 value)
{
- struct emac_eth_dev *priv = bus->priv;
- struct emac_regs *regs = priv->regs;
+ struct sun4i_mac_eth_dev *priv = bus->priv;
+ struct sun4i_mac_regs *regs = priv->regs;
/* issue the phy address and reg */
writel(addr << 8 | reg, ®s->mac_madr);
@@ -245,7 +249,7 @@ static int emac_mdio_write(struct mii_dev *bus, int addr,
int devad, int reg,
return 0;
}
-static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev)
+static int sun4i_mac_init_phy(struct sun4i_mac_eth_dev *priv, void *dev)
{
int ret, mask = 0xffffffff;
@@ -259,10 +263,10 @@ static int sunxi_emac_init_phy(struct emac_eth_dev *priv,
void *dev)
return -ENOMEM;
}
- priv->bus->read = emac_mdio_read;
- priv->bus->write = emac_mdio_write;
+ priv->bus->read = sun4i_mac_mdio_read;
+ priv->bus->write = sun4i_mac_mdio_write;
priv->bus->priv = priv;
- strcpy(priv->bus->name, "emac");
+ strcpy(priv->bus->name, "sun4i-mac");
ret = mdio_register(priv->bus);
if (ret)
@@ -279,43 +283,43 @@ static int sunxi_emac_init_phy(struct emac_eth_dev *priv,
void *dev)
return 0;
}
-static void emac_setup(struct emac_eth_dev *priv)
+static void sun4i_mac_setup(struct sun4i_mac_eth_dev *priv)
{
- struct emac_regs *regs = priv->regs;
+ struct sun4i_mac_regs *regs = priv->regs;
u32 reg_val;
/* Set up TX */
- writel(EMAC_TX_SETUP, ®s->tx_mode);
+ writel(SUN4I_MAC_TX_SETUP, ®s->tx_mode);
/* Set up RX */
- writel(EMAC_RX_SETUP, ®s->rx_ctl);
+ writel(SUN4I_MAC_RX_SETUP, ®s->rx_ctl);
/* Set MAC */
/* Set MAC CTL0 */
- writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0);
+ writel(SUN4I_MAC_MAC_CTL0_SETUP, ®s->mac_ctl0);
/* Set MAC CTL1 */
reg_val = 0;
if (priv->phydev->duplex == DUPLEX_FULL)
reg_val = (0x1 << 0);
- writel(EMAC_MAC_CTL1_SETUP | reg_val, ®s->mac_ctl1);
+ writel(SUN4I_MAC_MAC_CTL1_SETUP | reg_val, ®s->mac_ctl1);
/* Set up IPGT */
- writel(EMAC_MAC_IPGT, ®s->mac_ipgt);
+ writel(SUN4I_MAC_MAC_IPGT, ®s->mac_ipgt);
/* Set up IPGR */
- writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), ®s->mac_ipgr);
+ writel(SUN4I_MAC_MAC_NBTB_IPG2 | (SUN4I_MAC_MAC_NBTB_IPG1 << 8),
®s->mac_ipgr);
/* Set up Collison window */
- writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), ®s->mac_clrt);
+ writel(SUN4I_MAC_MAC_RM | (SUN4I_MAC_MAC_CW << 8), ®s->mac_clrt);
/* Set up Max Frame Length */
- writel(EMAC_MAC_MFL, ®s->mac_maxf);
+ writel(SUN4I_MAC_MAC_MFL, ®s->mac_maxf);
}
-static void emac_reset(struct emac_eth_dev *priv)
+static void sun4i_mac_reset(struct sun4i_mac_eth_dev *priv)
{
- struct emac_regs *regs = priv->regs;
+ struct sun4i_mac_regs *regs = priv->regs;
debug("resetting device\n");
@@ -327,9 +331,9 @@ static void emac_reset(struct emac_eth_dev *priv)
udelay(200);
}
-static int _sunxi_write_hwaddr(struct emac_eth_dev *priv, u8 *enetaddr)
+static int _sun4i_write_hwaddr(struct sun4i_mac_eth_dev *priv, u8 *enetaddr)
{
- struct emac_regs *regs = priv->regs;
+ struct sun4i_mac_regs *regs = priv->regs;
u32 enetaddr_lo, enetaddr_hi;
enetaddr_lo = enetaddr[2] | (enetaddr[1] << 8) | (enetaddr[0] << 16);
@@ -341,9 +345,9 @@ static int _sunxi_write_hwaddr(struct emac_eth_dev *priv,
u8 *enetaddr)
return 0;
}
-static int _sunxi_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
+static int _sun4i_mac_eth_init(struct sun4i_mac_eth_dev *priv, u8 *enetaddr)
{
- struct emac_regs *regs = priv->regs;
+ struct sun4i_mac_regs *regs = priv->regs;
int ret;
/* Init EMAC */
@@ -362,13 +366,13 @@ static int _sunxi_emac_eth_init(struct emac_eth_dev
*priv, u8 *enetaddr)
udelay(1);
/* Set up EMAC */
- emac_setup(priv);
+ sun4i_mac_setup(priv);
- _sunxi_write_hwaddr(priv, enetaddr);
+ _sun4i_write_hwaddr(priv, enetaddr);
mdelay(1);
- emac_reset(priv);
+ sun4i_mac_reset(priv);
/* PHY POWER UP */
ret = phy_startup(priv->phydev);
@@ -404,10 +408,10 @@ static int _sunxi_emac_eth_init(struct emac_eth_dev
*priv, u8 *enetaddr)
return 0;
}
-static int _sunxi_emac_eth_recv(struct emac_eth_dev *priv, void *packet)
+static int _sun4i_mac_eth_recv(struct sun4i_mac_eth_dev *priv, void *packet)
{
- struct emac_regs *regs = priv->regs;
- struct emac_rxhdr rxhdr;
+ struct sun4i_mac_regs *regs = priv->regs;
+ struct sun4i_mac_rxhdr rxhdr;
u32 rxcount;
u32 reg_val;
int rx_len;
@@ -448,7 +452,7 @@ static int _sunxi_emac_eth_recv(struct emac_eth_dev *priv,
void *packet)
*/
good_packet = 1;
- emac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr));
+ sun4i_mac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr));
rx_len = rxhdr.rx_len;
rx_status = rxhdr.rx_status;
@@ -460,37 +464,37 @@ static int _sunxi_emac_eth_recv(struct emac_eth_dev
*priv, void *packet)
}
/* rx_status is identical to RSR register. */
- if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) {
+ if (0 & rx_status & (SUN4I_MAC_CRCERR | SUN4I_MAC_LENERR)) {
good_packet = 0;
- if (rx_status & EMAC_CRCERR)
+ if (rx_status & SUN4I_MAC_CRCERR)
printf("crc error\n");
- if (rx_status & EMAC_LENERR)
+ if (rx_status & SUN4I_MAC_LENERR)
printf("length error\n");
}
/* Move data from EMAC */
if (good_packet) {
- if (rx_len > EMAC_RX_BUFSIZE) {
+ if (rx_len > SUN4I_MAC_RX_BUFSIZE) {
printf("Received packet is too big (len=%d)\n", rx_len);
return -EMSGSIZE;
}
- emac_inblk_32bit((void *)®s->rx_io_data, packet, rx_len);
+ sun4i_mac_inblk_32bit((void *)®s->rx_io_data, packet,
rx_len);
return rx_len;
}
return -EIO; /* Bad packet */
}
-static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet,
+static int _sun4i_mac_eth_send(struct sun4i_mac_eth_dev *priv, void *packet,
int len)
{
- struct emac_regs *regs = priv->regs;
+ struct sun4i_mac_regs *regs = priv->regs;
/* Select channel 0 */
writel(0, ®s->tx_ins);
/* Write packet */
- emac_outblk_32bit((void *)®s->tx_io_data, packet, len);
+ sun4i_mac_outblk_32bit((void *)®s->tx_io_data, packet, len);
/* Set TX len */
writel(len, ®s->tx_pl0);
@@ -501,13 +505,13 @@ static int _sunxi_emac_eth_send(struct emac_eth_dev
*priv, void *packet,
return 0;
}
-static void sunxi_emac_board_setup(struct emac_eth_dev *priv)
+static void sun4i_mac_board_setup(struct sun4i_mac_eth_dev *priv)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_sramc_regs *sram =
(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
- struct emac_regs *regs = priv->regs;
+ struct sun4i_mac_regs *regs = priv->regs;
int pin;
/* Map SRAM to EMAC */
@@ -524,67 +528,67 @@ static void sunxi_emac_board_setup(struct emac_eth_dev
*priv)
clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2);
}
-static int sunxi_emac_eth_start(struct udevice *dev)
+static int sun4i_mac_eth_start(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
- return _sunxi_emac_eth_init(dev->priv, pdata->enetaddr);
+ return _sun4i_mac_eth_init(dev->priv, pdata->enetaddr);
}
-static int sunxi_emac_eth_send(struct udevice *dev, void *packet, int length)
+static int sun4i_mac_eth_send(struct udevice *dev, void *packet, int length)
{
- struct emac_eth_dev *priv = dev_get_priv(dev);
+ struct sun4i_mac_eth_dev *priv = dev_get_priv(dev);
- return _sunxi_emac_eth_send(priv, packet, length);
+ return _sun4i_mac_eth_send(priv, packet, length);
}
-static int sunxi_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+static int sun4i_mac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
{
- struct emac_eth_dev *priv = dev_get_priv(dev);
+ struct sun4i_mac_eth_dev *priv = dev_get_priv(dev);
int rx_len;
- rx_len = _sunxi_emac_eth_recv(priv, priv->rx_buf);
+ rx_len = _sun4i_mac_eth_recv(priv, priv->rx_buf);
*packetp = priv->rx_buf;
return rx_len;
}
-static void sunxi_emac_eth_stop(struct udevice *dev)
+static void sun4i_mac_eth_stop(struct udevice *dev)
{
/* Nothing to do here */
}
-static int sunxi_emac_eth_probe(struct udevice *dev)
+static int sun4i_mac_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
- struct emac_eth_dev *priv = dev_get_priv(dev);
+ struct sun4i_mac_eth_dev *priv = dev_get_priv(dev);
- priv->regs = (struct emac_regs *)pdata->iobase;
- sunxi_emac_board_setup(priv);
+ priv->regs = (struct sun4i_mac_regs *)pdata->iobase;
+ sun4i_mac_board_setup(priv);
- return sunxi_emac_init_phy(priv, dev);
+ return sun4i_mac_init_phy(priv, dev);
}
-static int sunxi_emac_eth_write_hwaddr(struct udevice *dev)
+static int sun4i_mac_eth_write_hwaddr(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
- struct emac_eth_dev *priv = dev_get_priv(dev);
+ struct sun4i_mac_eth_dev *priv = dev_get_priv(dev);
if (!pdata)
return -ENOSYS;
- return _sunxi_write_hwaddr(priv, pdata->enetaddr);
+ return _sun4i_write_hwaddr(priv, pdata->enetaddr);
}
-static const struct eth_ops sunxi_emac_eth_ops = {
- .start = sunxi_emac_eth_start,
- .send = sunxi_emac_eth_send,
- .recv = sunxi_emac_eth_recv,
- .stop = sunxi_emac_eth_stop,
- .write_hwaddr = sunxi_emac_eth_write_hwaddr,
+static const struct eth_ops sun4i_mac_eth_ops = {
+ .start = sun4i_mac_eth_start,
+ .send = sun4i_mac_eth_send,
+ .recv = sun4i_mac_eth_recv,
+ .stop = sun4i_mac_eth_stop,
+ .write_hwaddr = sun4i_mac_eth_write_hwaddr,
};
-static int sunxi_emac_eth_ofdata_to_platdata(struct udevice *dev)
+static int sun4i_mac_eth_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
@@ -593,18 +597,18 @@ static int sunxi_emac_eth_ofdata_to_platdata(struct
udevice *dev)
return 0;
}
-static const struct udevice_id sunxi_emac_eth_ids[] = {
+static const struct udevice_id sun4i_mac_eth_ids[] = {
{ .compatible = "allwinner,sun4i-a10-emac" },
{ }
};
-U_BOOT_DRIVER(eth_sunxi_emac) = {
- .name = "eth_sunxi_emac",
+U_BOOT_DRIVER(eth_sun4i_mac) = {
+ .name = "eth_sun4i_mac",
.id = UCLASS_ETH,
- .of_match = sunxi_emac_eth_ids,
- .ofdata_to_platdata = sunxi_emac_eth_ofdata_to_platdata,
- .probe = sunxi_emac_eth_probe,
- .ops = &sunxi_emac_eth_ops,
- .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
+ .of_match = sun4i_mac_eth_ids,
+ .ofdata_to_platdata = sun4i_mac_eth_ofdata_to_platdata,
+ .probe = sun4i_mac_eth_probe,
+ .ops = &sun4i_mac_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct sun4i_mac_eth_dev),
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
};
--
2.11.0
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