During a quick search I had not been able to find any HDMI CEC driver. In
the docs available there is only one Register about CEC.
I thought about implementation of an driver and libcec support for the A20.
Regards,
Christian
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пятница, 3 октября 2014 г., 21:12:33 UTC+3 пользователь Christian Ege написал:
> Hi,
>
> Am 03.10.2014 um 09:56 schrieb Vladimir Komendantskiy:
>
>
>
>
> The Allwinner SoCs that have an HDMI pin, also have
> a memory-mapped HDMI-CEC register located at HDMI base
>
Hi,
sorry for bringing this thread back to live but was there any progress
around with CEC and A20 chips? I can not find anything on the net so I was
wondering if any of you guys managed to get any further.
El viernes, 26 de febrero de 2016, 14:38:33 (UTC+1), dk.u...@gmail.com
escribió:
>
> пя
I
On Thu, Oct 2, 2014 at 1:19 PM, Christian Ege wrote:
> During a quick search I had not been able to find any HDMI CEC driver. In
> the docs available there is only one Register about CEC.
>
> I thought about implementation of an driver and libcec support for the A20.
I believe CEC is just I2C
I'm working on a generic bit-banging CEC kernel driver for A10s/A20. Those
have only one pin exposed. All control and timing is done in software
according to the CEC addendum in the HDMI 1.4 specification.
This is unlike in NVidia Tegra for example which has a proper hardware CEC
controller.
--Vl
Hi,
On Fri, Oct 3, 2014 at 3:29 AM, jonsm...@gmail.com wrote:
> I
>
> On Thu, Oct 2, 2014 at 1:19 PM, Christian Ege wrote:
>> During a quick search I had not been able to find any HDMI CEC driver. In
>> the docs available there is only one Register about CEC.
>>
>> I thought about implementation
The Allwinner SoCs that have an HDMI pin, also have a memory-mapped
HDMI-CEC register located at HDMI base 0xf1c16000 plus the offset 0x214.
This register provides the following bits
#define CEC_RX 0x0100 /* phys. line value, either high or low */
#define CEC_TX 0x0200
#define CEC_ENABLE
Hi,
Am 03.10.2014 um 09:56 schrieb Vladimir Komendantskiy:
The Allwinner SoCs that have an HDMI pin, also have a memory-mapped
HDMI-CEC register located at HDMI base 0xf1c16000 plus the offset
0x214. This register provides the following bits
#define CEC_RX 0x0100 /* phys. line value, eith
