Hi Jens,
My H3 machine (OPI2) cannot boot with the PLL6 (periph0) as defined
in the kernel 4.5-rc1. As there is no UART, I don't know what is wrong.
But, applying your old patch
[PATCH v4 1/6] clk: sunxi: Let divs clocks read the base factor clock name from
devicetree
(https://lkml.org/lkml/201
Hi,
On Wed, Jan 27, 2016 at 3:46 PM, Jean-Francois Moine wrote:
> Hi Jens,
>
> My H3 machine (OPI2) cannot boot with the PLL6 (periph0) as defined
> in the kernel 4.5-rc1. As there is no UART, I don't know what is wrong.
>
> But, applying your old patch
>
> [PATCH v4 1/6] clk: sunxi: Let divs clo
On Wed, 27 Jan 2016 16:18:53 +0800
Chen-Yu Tsai wrote:
> Hi,
Hi ChenYu,
> On Wed, Jan 27, 2016 at 3:46 PM, Jean-Francois Moine wrote:
> > Hi Jens,
> >
> > My H3 machine (OPI2) cannot boot with the PLL6 (periph0) as defined
> > in the kernel 4.5-rc1. As there is no UART, I don't know what is wr
On 27/01/16 10:37, Jean-Francois Moine wrote:
> On Wed, 27 Jan 2016 16:18:53 +0800
> Chen-Yu Tsai wrote:
>
>> Hi,
>
> Hi ChenYu,
>
>> On Wed, Jan 27, 2016 at 3:46 PM, Jean-Francois Moine wrote:
>>> Hi Jens,
>>>
>>> My H3 machine (OPI2) cannot boot with the PLL6 (periph0) as defined
>>> in the
On Wed, 27 Jan 2016 15:36:21 +0100
Jens Kuske wrote:
> That sounds strange, 4.5-rc1 is working perfectly fine for me too.
>
> I doubt the patch you linked is responsible for making it work, it only
> removes the hardcoded output-names. If your DT isn't messed up this
> isn't relevant at all sinc
Hi,
On 27-01-16 17:55, Jean-Francois Moine wrote:
On Wed, 27 Jan 2016 15:36:21 +0100
Jens Kuske wrote:
That sounds strange, 4.5-rc1 is working perfectly fine for me too.
I doubt the patch you linked is responsible for making it work, it only
removes the hardcoded output-names. If your DT isn
On Wed, 27 Jan 2016 19:16:42 +0100
Hans de Goede wrote:
> > To be sure, I generated a pure 4.5-rc1 kernel. Same result: no UART.
> > Maybe... one more information: I am using Allwinner's u-boot.
>
> Could be that that is the culprit, why are you not using upstream u-boot?
> upstream u-boot has H
Hi,
On 27-01-16 20:02, Jean-Francois Moine wrote:
On Wed, 27 Jan 2016 19:16:42 +0100
Hans de Goede wrote:
To be sure, I generated a pure 4.5-rc1 kernel. Same result: no UART.
Maybe... one more information: I am using Allwinner's u-boot.
Could be that that is the culprit, why are you not usi
On 28/01/16 09:15, Hans de Goede wrote:
> Hi,
>
> On 27-01-16 20:02, Jean-Francois Moine wrote:
>> On Wed, 27 Jan 2016 19:16:42 +0100
>> Hans de Goede wrote:
>>
To be sure, I generated a pure 4.5-rc1 kernel. Same result: no UART.
Maybe... one more information: I am using Allwinner's u-b
On Thu, 28 Jan 2016 09:15:57 +0100
Hans de Goede wrote:
> p.s.
>
> Did I understand correctly that you are working on a kms (or fbdev) driver
> for the H3? A fellow Dutch hacker (Jelle van der Waa, added to the Cc) is
> looking into adding H3 video console support to upstream u-boot. If you
> al
On Thu, 28 Jan 2016 14:16:26 +0100
Jens Kuske wrote:
> after figuring out how to boot a devicetree kernel with allwinner's
> u-boot I only had to add the mandatory
>
> clock-frequency = <2400>;
> arm,cpu-registers-not-fw-configured;
>
> to the timer node and v4.5-rc1 boote
On Thu, Jan 28, 2016 at 09:15:57AM +0100, Hans de Goede wrote:
> Hi,
>
> On 27-01-16 20:02, Jean-Francois Moine wrote:
> >On Wed, 27 Jan 2016 19:16:42 +0100
> >Hans de Goede wrote:
> >
> >>>To be sure, I generated a pure 4.5-rc1 kernel. Same result: no UART.
> >>>Maybe... one more information: I
On Thu, Jan 28, 2016 at 05:59:18PM +0100, Jean-Francois Moine wrote:
> On Thu, 28 Jan 2016 14:16:26 +0100
> Jens Kuske wrote:
>
> > after figuring out how to boot a devicetree kernel with allwinner's
> > u-boot I only had to add the mandatory
> >
> > clock-frequency = <2400>;
> >
Hi,
On 01/28/2016 08:29 PM, Maxime Ripard wrote:
On Thu, Jan 28, 2016 at 05:59:18PM +0100, Jean-Francois Moine wrote:
The A23/A33/H3 (and surely some other SoCs) documentations about
the peripheral/periph/periph0/periph1 PLLs say:
Note: The PLL Output should be fixed to 600MHz, it
On Thu, 28 Jan 2016 20:29:31 +0100
Maxime Ripard wrote:
> > You are right, I had these lines in my DT. Thanks.
>
> And even though you had these lines, it was still not working? Or is
> it working now? I'm confused.
It was not working with these lines because I was using the real pll8,
and, so,
On Fri, Jan 29, 2016 at 2:25 PM, Hans de Goede wrote:
> Hi,
>
> On 01/28/2016 08:29 PM, Maxime Ripard wrote:
>>
>> On Thu, Jan 28, 2016 at 05:59:18PM +0100, Jean-Francois Moine wrote:
>
>
>
>
>>> The A23/A33/H3 (and surely some other SoCs) documentations about
>>> the peripheral/periph/periph0/pe
Hi,
On Fri, Jan 29, 2016 at 07:25:51AM +0100, Hans de Goede wrote:
> Hi,
>
> On 01/28/2016 08:29 PM, Maxime Ripard wrote:
> >On Thu, Jan 28, 2016 at 05:59:18PM +0100, Jean-Francois Moine wrote:
>
>
>
> >>The A23/A33/H3 (and surely some other SoCs) documentations about
> >>the peripheral/periph
Hi,
On 01-02-16 07:37, Maxime Ripard wrote:
Hi,
On Fri, Jan 29, 2016 at 07:25:51AM +0100, Hans de Goede wrote:
Hi,
On 01/28/2016 08:29 PM, Maxime Ripard wrote:
On Thu, Jan 28, 2016 at 05:59:18PM +0100, Jean-Francois Moine wrote:
The A23/A33/H3 (and surely some other SoCs) documentations
Hi,
On Mon, Feb 1, 2016 at 10:26 PM, Hans de Goede wrote:
> Hi,
>
>
> On 01-02-16 07:37, Maxime Ripard wrote:
>>
>> Hi,
>>
>> On Fri, Jan 29, 2016 at 07:25:51AM +0100, Hans de Goede wrote:
>>>
>>> Hi,
>>>
>>> On 01/28/2016 08:29 PM, Maxime Ripard wrote:
On Thu, Jan 28, 2016 at 05:59:18P
On Mon, Feb 01, 2016 at 10:37:45PM +0800, Chen-Yu Tsai wrote:
> >> There is, but it's opt-in, and we're not using it yet for anything but
> >> the hstimers (and in that case, we don't prevent the reclocking, we
> >> just take it into account).
> >
> > Shouldn't we be opt-ing in then ? At least the
On Mon, Feb 01, 2016 at 03:26:43PM +0100, Hans de Goede wrote:
> >There is, but it's opt-in, and we're not using it yet for anything but
> >the hstimers (and in that case, we don't prevent the reclocking, we
> >just take it into account).
>
> Shouldn't we be opt-ing in then ? At least the mmc driv
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