On Wed, Jan 28, 2015 at 03:54:07AM +0800, Chen-Yu Tsai wrote: > The USB controller/phy clocks and reset controls are in a separate > address block, unlike previous SoCs where they were in the clock > controller. Also, access to the address block is controlled by a > clock gate to AHB. > > Add support for resets requiring a clock to be enabled when > asserting/deasserting the reset controls, and add the sun9i USB > clocks. > > Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Applied, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
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