cific glue layer.
MFD_AXP20X and the new MFD_AXP20X_I2C are changed to tristate
symbols, allowing the driver to be built as modules.
Included but unused header files are removed as well.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/mfd/Kconfig| 14 +++--
drivers/mfd/Make
On Mon, Nov 23, 2015 at 6:50 PM, Hans de Goede wrote:
> HI,
>
>
> On 23-11-15 09:57, Maxime Ripard wrote:
>>
>> Hi,
>>
>> On Sun, Nov 01, 2015 at 02:33:23PM +0100, Jens Kuske wrote:
>
> + bus_gates: clk@01c20060 {
> +
hese types of clocks, which also includes the AHB clock
driver on sun[5678]i.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
Hi Maxime,
I'll do the factors clock refactoring mentioned during the discussion
around v2 later on.
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
d
The main (24MHz) clock on the A80 is configurable via the PRCM address
space. The low power/speed (32kHz) clock is from an external chip, the
AC100.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun9i-a80.dtsi | 18 ++
1 file changed, 18 insertions(+)
This patch adds support for the PRCM apbs clock gates found on the
Allwinner A80 SoC.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-simple-gates.c | 2 ++
2 files changed, 3 insertions(+)
diff
.
Also, build it for all Allwinner/sunxi platforms, and not just for
configurations with MFD_SUN6I_PRCM enabled.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/clk/sunxi/Makefile | 4 ++--
drivers/clk/sunxi/clk-sun8i-apb0.c | 43 ++
2 files c
This adds the supported PRCM clocks and reset controls to the A80 dtsi.
The DAUDIO module clocks are not supported yet.
Also update clock and reset phandles for r_uart.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun9i-a80.dts
On Tue, Nov 24, 2015 at 8:35 PM, Andy Shevchenko
<andy.shevche...@gmail.com> wrote:
> On Tue, Nov 24, 2015 at 1:28 PM, Chen-Yu Tsai <w...@csie.org> wrote:
>> Hi,
>>
>> On Tue, Nov 24, 2015 at 5:37 PM, Andy Shevchenko
>> <andy.shevche...@gmail.com> wro
Hi,
On Tue, Nov 24, 2015 at 5:37 PM, Andy Shevchenko
<andy.shevche...@gmail.com> wrote:
> On Tue, Nov 24, 2015 at 5:48 AM, Chen-Yu Tsai <w...@csie.org> wrote:
>> The axp20x driver assumes the device is i2c based. This is not the
>> case with later chips, which use a pr
adds an RSB based driver for the AXP223.
Patch 8 adds support for the AXP223 regulators
Patch 9 enables the AXP223 PMIC and its regulators for the Sinlinx
SinA33.
Patch 10 enables the AXP223 PMIC and its regulators for A23/A33 based
Q8 tablet devices.
Regards
ChenYu
Chen-Yu Tsai (10):
mfd: axp20
.
of_device_get_match_data() cannot be used here as we need to know if
it failed to get a match, or if the match data value just happened to
be 0, as it is for the AXP152.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
drivers/mfd/axp20x.c | 2 +-
1 fil
<andy.shevche...@gmail.com>
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
drivers/mfd/axp20x.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 9842199e2e6c..6
The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Reviewed-by: Mark Brown <broo...@k
The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
Changes since v6:
- Drop filename fro
This fixes some leftover code style issues in the axp20x core.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
drivers/mfd/axp20x.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mfd/axp20x.c b/drivers/
This board has a X-Powers AXP223 PMIC connected via RSB. Its regulators
provide power to various parts of the SoC and the board.
Also update the regulator supply phandles.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dt
A23/A33 Q8 tablets have an X-Powers AXP223 PMIC connected via RSB. Its
regulators provide power to various parts of the SoC and the board.
Also add lcd regulator supply for simplefb and update the existing
vmmc-supply for mmc0.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/bo
.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
board/sunxi/board.c| 8 +++-
drivers/power/Kconfig | 13 ++---
drivers/power/axp818.c | 37 +
3 files changed, 50 insertions(+), 8 deletions(-)
diff --git a/board/sunxi/board.c b/board
AXP818 provides an array of LDOs to provide power to various peripherals.
None of these regulators are critical.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/power/Kconfig | 12 ++--
drivers/power/axp818.c | 44
2 files chang
Some of the register definitions are duplicated. Drop them.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
include/axp818.h | 8
1 file changed, 8 deletions(-)
diff --git a/include/axp818.h b/include/axp818.h
index 1dc6456..46d05ad 100644
--- a/include/axp818.h
+++ b/include/ax
Hi,
On Mon, Jan 11, 2016 at 5:25 PM, Lee Jones <lee.jo...@linaro.org> wrote:
> On Thu, 17 Dec 2015, Chen-Yu Tsai wrote:
>
>> The axp20x driver assumes the device is i2c based. This is not the
>> case with later chips, which use a proprietary 2 wire serial bus
>>
On Tue, Jan 12, 2016 at 10:08 PM, Benjamin Henrion wrote:
> On Tue, Jan 12, 2016 at 3:05 PM, Benjamin Henrion wrote:
>> Looking at fosdem talks, I found this project:
>>
>> https://fosdem.org/2016/schedule/event/kernelci/
>> http://kernelci.org/soc/sunxi/
>>
Hi,
On Sat, Jun 4, 2016 at 6:01 PM, Jean-Francois Moine wrote:
> The A83T has different clock delays.
> The values have been adapted from the Banana Pi M3 driver.
>
> Signed-off-by: Jean-Francois Moine
> ---
>
Hi,
On Fri, Jun 3, 2016 at 7:16 PM, Jean-Francois Moine <moin...@free.fr> wrote:
> Hi Wens,
>
> Thanks for the review.
>
> On Fri, 3 Jun 2016 14:53:24 +0800
> Chen-Yu Tsai <w...@csie.org> wrote:
>
>> On Tue, May 31, 2016 at 3:26 PM, Jean-Francois Moine
Hi,
On Tue, May 31, 2016 at 3:26 PM, Jean-Francois Moine wrote:
> The A83T and A80 SoCs have unique settings of their PLL clocks.
>
> Signed-off-by: Jean-Francois Moine
> ---
> drivers/clk/sunxi-ng/ccu_ndmp.c | 247
>
>
Hi Rob,
On Thu, Jun 9, 2016 at 3:11 AM, Rob Herring wrote:
> On Mon, Jun 06, 2016 at 08:10:54PM +0200, Corentin LABBE wrote:
>> Le 06/06/2016 16:14, Rob Herring a écrit :
>> > On Fri, Jun 03, 2016 at 11:56:28AM +0200, LABBE Corentin wrote:
>> >> This patch adds documentation for
Hi,
On Tue, May 31, 2016 at 3:43 AM, Maxime Ripard
wrote:
> Hi,
>
> On Mon, May 30, 2016 at 08:30:13PM +0800, luoyi...@gmail.com wrote:
>> From: luoyi
>>
>> Add support for the Bananapi M1 Plus A20 development board from
>> sinovoip.com.cn
Hi everyone,
This series adds support for Sinovoip's BPI-M2+, an Allwinner H3 SoC based
development board. It is a smaller form factor than the original BPI-M2,
which was based on a different SoC.
The patches are pretty self-explaining.
Regards
ChenYu
Chen-Yu Tsai (3):
ARM: dts: sun8i-h3
Add uart1 pins for 4 pin (RX/TX/RTS/CTS) mode.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 52558046dbaf..3c37f7e2b079
header for (debug) UART, a 40 pin GPIO header
based on the Raspberry Pi B+, but the peripheral signals are not the
same, and an FPC connector for connecting BPI's camera.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/Makefile | 3 +-
.../arm/bo
Move uart0 pins to sort the list of pin settings in alphabetical order.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/su
Hi,
On Wed, Jun 22, 2016 at 1:02 AM, wrote:
> Hi All,
>
> I couldn't find sunxi-next branch that include hypervisor support in current
> git repo ( git://github.com/jwrdegoede/u-boot-sunxi.git). Please let me know
> if what is correct branch i need to use for creating
On Sun, Jun 19, 2016 at 4:14 AM, Stefan Monnier
wrote:
>> My cubietruck with battery and Samsung HDD has been up for 79 days using
>> this power supply:
>
> BTW, by "reliability" I don't mean "time between reboots" but "time
> before hardware failure". So far my
On Mon, Jun 20, 2016 at 2:42 PM, Stefan Mavrodiev
wrote:
> A33-OLinuXino is A33 development board designed by Olimex LTD.
>
> It has AXP233 PMU, 1GB DRAM, a micro SD card, one USB-OTG connector,
> headphone and mic jacks, connector for LiPo battery and optional
> 4GB
Hi,
On Mon, Jun 13, 2016 at 3:40 PM, Maxime Ripard
wrote:
> On Thu, Jun 09, 2016 at 10:34:40AM +0200, Hans de Goede wrote:
>> Hi,
>>
>> On 09-06-16 09:53, Maxime Ripard wrote:
>> >Hi Hans,
>> >
>> >On Sat, Jun 04, 2016 at 08:10:54PM +0200, Hans de Goede wrote:
On Fri, Jun 24, 2016 at 3:21 AM, wrote:
> From: Ondrej Jirman
>
> Add sy8106a regulator to r_twi bus on Orange Pi PC. This
> regulator controls the CPUX voltage.
>
> Signed-off-by: Ondrej Jirman
> ---
>
On Fri, Jun 24, 2016 at 3:20 AM, wrote:
> From: Josef Gajdusek
>
> Add a node describing the Security ID memory to the Allwinner H3 .dtsi file.
>
> Signed-off-by: Josef Gajdusek
> ---
> arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++
> 1 file
On Fri, Jun 24, 2016 at 3:20 AM, wrote:
> From: Ondrej Jirman
>
> This patch adds the binding documentation for the sun8i_ths driver
>
> Signed-off-by: Ondřej Jirman
> ---
> .../devicetree/bindings/thermal/sun8i-ths.txt | 31
>
Hi,
On Fri, Jun 24, 2016 at 3:20 AM, wrote:
> From: Ondrej Jirman
>
The subject could read:
thermal: sun8i_ths: Add support for the thermal sensor on Allwinner H3
> This patch adds support for the sun8i thermal sensor on
> Allwinner H3 SoC.
>
>
On Fri, Jun 24, 2016 at 3:20 AM, wrote:
> From: Ondrej Jirman
>
> SY8106A is I2C attached single output voltage regulator
> made by Silergy.
>
> Signed-off-by: Ondrej Jirman
> ---
> drivers/regulator/Kconfig | 8 +-
>
On Fri, Jun 24, 2016 at 3:20 AM, wrote:
> From: Ondrej Jirman
>
> Add label to the first cpu so that it can be referenced
> from derived dts files.
>
> Signed-off-by: Ondrej Jirman
> ---
> arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
> 1
On Mon, Jan 11, 2016 at 8:09 PM, Lee Jones <lee.jo...@linaro.org> wrote:
> On Mon, 11 Jan 2016, Chen-Yu Tsai wrote:
>> On Mon, Jan 11, 2016 at 5:24 PM, Lee Jones <lee.jo...@linaro.org> wrote:
>> > On Thu, 17 Dec 2015, Chen-Yu Tsai wrote:
>> >
>>
On Mon, Jan 18, 2016 at 3:48 AM, David Keaney wrote:
> I have built a basic kernel following the Mailine Kernel Howto and have it
> working on my board but now I'm trying to compile a kernel
> with 'Enable loadable module support' enabled and this is where I'm running
>
Hi,
On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
wrote:
> The A10 SoCs and its relatives has a special clock controller to drive the
> display engines (both frontend and backend), that have a lot in common with
> the clock to drive the first TCON channel.
>
>
Hi,
On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
wrote:
> The TCON is a controller generating the timings to output videos signals,
> acting like both a CRTC and an encoder.
>
> It has two channels depending on the output, each channel being driven by
> its
On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
wrote:
> The DRAM gates control whether the image / display devices on the SoC have
> access to the DRAM clock or not.
>
> Enable it.
>
> Signed-off-by: Maxime Ripard
> ---
>
Hi,
On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
wrote:
> Enable the display and TCON (channel 0 and channel 1) clocks that are going
> to be needed to drive the display engine, tcon and TV encoders.
>
> Signed-off-by: Maxime Ripard
clk_name);
> + goto err_free_mult;
> + }
> +
> + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
> + if (WARN_ON(ret))
Any particular reason for WARN_ON instead of pr_err like above?
> + goto err_clk_unregister;
>
which holds the MAC address.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 65
2 files changed, 66 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8
The A83T, like previous Allwinner SoCs, has a watchdog as part of its
timer block. Add a device node for it.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/ar
watchdog and reboot support
on the A83T.
Patch 3 adds a basic DTS file for the Cubieteuck Plus.
Chen-Yu Tsai (2):
ARM: dts: sun8i: Add watchdog device node for A83T
ARM: dts: sun8i: Add device tree for Cubietruck Plus
Vishnu Patekar (1):
ARM: dts: sun8i: Enable timer node for A83T
arch/arm/boot
From: Vishnu Patekar <vishnupatekar0...@gmail.com>
A83T timer is compatible with that of earlier SOCs.
Just add timer node to enable and re-use it.
Signed-off-by: Vishnu Patekar <vishnupatekar0...@gmail.com>
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/s
On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> It turns out that the A13 / R8 also have a tve encoder block, and a gate
> for it.
>
> Add it to the DT.
>
> Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com&
On Sat, Jun 25, 2016 at 8:11 AM, Ondřej Jirman <meg...@megous.com> wrote:
> Hi,
>
> thank you for the review. I've resolved most of the issues. Some more
> comments below.
>
> On 24.6.2016 05:41, Chen-Yu Tsai wrote:
>> On Fri, Jun 24, 2016 at 3:20 AM, <meg...@me
On Sat, Jun 25, 2016 at 6:51 AM, Ondřej Jirman <meg...@megous.com> wrote:
> Hello,
>
> comments below.
>
> On 24.6.2016 05:48, Chen-Yu Tsai wrote:
>> On Fri, Jun 24, 2016 at 3:20 AM, <meg...@megous.com> wrote:
>>> From: Ondrej Jirman <meg...@mego
Hi,
On Sat, Jun 25, 2016 at 3:58 AM, Ondřej Jirman <meg...@megous.com> wrote:
> Hello,
>
> thank you for the review.
>
> On 24.6.2016 04:41, Chen-Yu Tsai wrote:
>> On Fri, Jun 24, 2016 at 3:20 AM, <meg...@megous.com> wrote:
>>> From: Josef Gajdusek <
On Thu, Jun 16, 2016 at 4:52 AM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> Hi Chen-Yu,
>
> On Mon, Jun 13, 2016 at 11:01:53AM +0800, Chen-Yu Tsai wrote:
>> On Fri, Jun 10, 2016 at 5:38 PM, Maxime Ripard
>> <maxime.rip...@free-electrons.com> wrote:
&
Hi,
On Wed, Jun 1, 2016 at 10:40 AM, luoyi wrote:
> This is the new version of the patch. and I think maybe every board
> should have their own dtb files. and we can you some cpp macro tricks
> to merge their coressponding dts file.
>
> diff --git
sunxi_defconfig already enables INPUT_AXP20X_PEK, but the device is not
exposed to userspace. Enable INPUT_EVDEV so it is.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/configs/sunxi_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/sunxi_defconfig
A consumer IR receiver is commonly found on Allwinner SoC based
development boards and set top boxes. The driver has been available
for some time. Enable it by default.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/configs/sunxi_defconfig | 4
1 file changed, 4 inse
, because for tablets
this is likely the only option for external USB peripherals.
Regards
ChenYu
Chen-Yu Tsai (6):
ARM: sunxi_defconfig: Enable sunxi IR driver
ARM: sunxi_defconfig: Enable A10 audio codec driver
ARM: sunxi_defconfig: Enable MUSB HDRC driver with Allwinner glue
ARM
.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/configs/sunxi_defconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index efa12c88fe1c..e29b81694184 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/ar
The A10 audio codec driver supports the on-chip audio codec found on
Allwinner A10, A10s, A13, A20 SoCs.
Build it as a module, since it is not critical.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
support.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/configs/multi_v7_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index 03703b7ea530..b500f18d0c35 100644
--- a/arch/arm/c
The A10 audio codec driver supports the on-chip audio codec found on
Allwinner A10, A10s, A13, A20 SoCs.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/configs/sunxi_defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/c
On Tue, Feb 2, 2016 at 8:17 PM, Mark Brown <broo...@kernel.org> wrote:
> On Tue, Feb 02, 2016 at 06:27:40PM +0800, Chen-Yu Tsai wrote:
>
>> + reg_dcdc1: dcdc1 {
>> + regulator-name = "dcdc1";
>> + };
>
&
On Tue, Feb 9, 2016 at 12:22 AM, Mark Brown <broo...@kernel.org> wrote:
> On Mon, Feb 08, 2016 at 10:56:05PM +0800, Chen-Yu Tsai wrote:
>> On Mon, Feb 8, 2016 at 10:53 PM, Mark Brown <broo...@kernel.org> wrote:
>> > On Sat, Feb 06, 2016 at 08:42:24PM +0800, Chen-Yu T
On Mon, Feb 8, 2016 at 10:53 PM, Mark Brown <broo...@kernel.org> wrote:
> On Sat, Feb 06, 2016 at 08:42:24PM +0800, Chen-Yu Tsai wrote:
>
>> Mark, may I assume you are OK with this DTS include listing
>> the regulators, even if their sections are empty?
>
> If it ha
On Tue, Feb 9, 2016 at 4:15 PM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> Hi,
>
> On Sat, Feb 06, 2016 at 11:53:46PM +0800, Chen-Yu Tsai wrote:
>> Allwinner SoCs typically have a Mentor Graphics Inventra MUSB dual role
>> controller for USB OTG.
>>
by: Krzysztof Adamski <k...@japko.eu>
Acked-by: Chen-Yu Tsai <w...@csie.org>
(resent as my mail setup failed to deliver)
--
You received this message because you are subscribed to the Google Groups
"linux-sunxi" group.
To unsubscribe from this group and stop receiv
On Thu, Feb 4, 2016 at 4:31 AM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> Hi,
>
> On Sun, Jan 17, 2016 at 01:06:07AM +0800, Chen-Yu Tsai wrote:
>> > + compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
>> > +
, since this was introduced in 4.5-rc1, please apply this series
for 4.5 so we fix it before the release.
Changes since v1:
- Replace the CLK_OF_DECLARE version of sun8i-a23-apb0-clk with the
A80 APBS version, instead of writing a new driver.
Regards
ChenYu
Chen-Yu Tsai (2):
clk: sunxi
A80's APBS clock is not the same as the APB0 clock on A23. The A80's
is a zero-based divider, while the A23's is a power-of-two divider.
Replace the CLK_OF_DECLARE version of sun8i-a23-apb0. This also extends
the common setup function to take div clk flags.
Signed-off-by: Chen-Yu Tsai &l
The APBS clock on A80 is not compatible with A23's APB0 clock. The only
reason it works is becase the lowest and default divider is the same.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Sat, Feb 13, 2016 at 12:06 AM, Vishnu Patekar
<vishnupatekar0...@gmail.com> wrote:
> Hello Wens,
>
>
> On Tue, Feb 2, 2016 at 2:44 PM, Chen-Yu Tsai <w...@csie.org> wrote:
>> On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
>> <vishnupatekar0...@gmail.com&
Hi,
On Thu, Feb 11, 2016 at 9:17 PM, Linus Walleij wrote:
> On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski wrote:
>
>> sunxi_pmx_set accepts pin number and then calculates offset by
>> subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the
The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Maxime Ripard <maxime.ri
A23/A33 Q8 tablets have an X-Powers AXP223 PMIC connected via RSB. Its
regulators provide power to various parts of the SoC and the board.
Also add lcd regulator supply for simplefb and update the existing
vmmc-supply for mmc0.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/bo
cific glue layer.
MFD_AXP20X and the new MFD_AXP20X_I2C are changed to tristate
symbols, allowing the driver to be built as modules.
Whitespace and other style errors in the moved i2c specific code
have been fixed. Included but unused header files are removed as
well.
Signed-off-by: Chen-Yu Tsai <
<andy.shevche...@gmail.com>
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
drivers/mfd/axp20x.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 9842199e2e6c..6
Supply a backdated copyright notice.
Cc: Carlo Caione <ca...@caione.org>
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Carlo Caione <ca...@caione.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
drivers/mfd/axp20x.c | 2 ++
1 file changed, 2 insertions(+)
This fixes some leftover code style issues in the axp20x core.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
drivers/mfd/axp20x.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mfd/axp20x.c b/drivers/
The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Lee Jones <lee.jo...@l
ors for A23/A33 based
Q8 tablet devices.
Regards
ChenYu
Chen-Yu Tsai (10):
mfd: axp20x: Add AXP223 to list of supported PMICs in DT bindings
mfd: axp20x: Remove second struct device * parameter for
axp20x_match_device()
mfd: axp20x: use dev->driver->of_match_table in axp20x_match_de
.
of_device_get_match_data() cannot be used here as we need to know if
it failed to get a match, or if the match data value just happened to
be 0, as it is for the AXP152.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
drivers/mfd/axp20x.c | 2 +-
1 fil
The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Reviewed-by: Mark Brown <broo...@k
This board has a X-Powers AXP223 PMIC connected via RSB. Its regulators
provide power to various parts of the SoC and the board.
Also update the regulator supply phandles.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dt
On Thu, Feb 11, 2016 at 11:24 PM, Lee Jones <lee.jo...@linaro.org> wrote:
> On Mon, 25 Jan 2016, Lee Jones wrote:
>
>> On Wed, 13 Jan 2016, Chen-Yu Tsai wrote:
>>
>> > When the driver was merged, the original author did not include a proper
>> > co
On Mon, Feb 1, 2016 at 12:59 AM, Paul Gortmaker
<paul.gortma...@windriver.com> wrote:
> On Mon, Jan 25, 2016 at 8:15 AM, Chen-Yu Tsai <w...@csie.org> wrote:
>> sun6i's AR100 clock is a classic factors clk case:
>>
>> AR100 = ((parent mux) >> p) / (m +
On Thu, Feb 4, 2016 at 7:33 AM, Krzysztof Adamski wrote:
> Add the corresponding device node for R_PIO on H3 to the dtsi. Support
> for the controller was added in earlier commit.
>
> Signed-off-by: Krzysztof Adamski
> ---
> arch/arm/boot/dts/sun8i-h3.dtsi | 12
s does not contain their value. When
>> value is read, GPIO function must be temporary switched to input for
>> reads.
>>
>> Signed-off-by: Krzysztof Adamski <k...@japko.eu>
>
> 1. Waiting for Maxime's ACK on this patch.
Maxime already acked v1.
Acked-by: Chen-
On Fri, Jan 29, 2016 at 6:42 PM, Ulf Hansson <ulf.hans...@linaro.org> wrote:
> On 21 January 2016 at 06:26, Chen-Yu Tsai <w...@csie.org> wrote:
>> Allwinner's mmc controller supports signal voltage switching. This is
>> supported in code in Allwinner's kernel. However, p
On Fri, Jan 29, 2016 at 2:25 PM, Hans de Goede wrote:
> Hi,
>
> On 01/28/2016 08:29 PM, Maxime Ripard wrote:
>>
>> On Thu, Jan 28, 2016 at 05:59:18PM +0100, Jean-Francois Moine wrote:
>
>
>
>
>>> The A23/A33/H3 (and surely some other SoCs) documentations about
>>> the
signal voltage switching (CMD11)".
According to Ulf, the mmc core won't send this command unless the UHS
capabilities are set. We don't.
- Increased f_max to 52 MHz. Clock rate range for 50 MHz timing delay
also increased to match. See patch 1.
Regards
ChenYu
Chen-Yu Tsai (3):
Now that clock delay settings for 8 bit DDR are correct, and vqmmc
support is available, we can enable MMC_CAP_1_8V_DDR support. This
enables MMC HS-DDR at up to 52 MHz, even if signal voltage switching
is not available.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
There was discussion
bit and 8 bit are shared. The new values for the other SoCs were from
A83T user manual's "new timing mode" default values, which describes
them in clock phase, rather than delay periods. These values were used
without any modification. They may not be correct, but they work.
Signed-off-b
-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/mmc/host/sunxi-mmc.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 765dfb9f77ec..fe6c171fd135 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drive
Hi,
On Thu, Jan 28, 2016 at 1:49 AM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> On Mon, Jan 25, 2016 at 09:15:47PM +0800, Chen-Yu Tsai wrote:
>> sun8i-a23-mbus-clk used sunxi's factors clk, which is nice for very
>> complicated clocks, but is not really neede
Hi,
On Wed, Jan 27, 2016 at 3:46 PM, Jean-Francois Moine wrote:
> Hi Jens,
>
> My H3 machine (OPI2) cannot boot with the PLL6 (periph0) as defined
> in the kernel 4.5-rc1. As there is no UART, I don't know what is wrong.
>
> But, applying your old patch
>
> [PATCH v4 1/6] clk:
RL_SUN8I_A83T_R
> + def_bool MACH_SUN8I
> + depends on RESET_CONTROLLER
> + select PINCTRL_SUNXI_COMMON
> +
Keep them sorted please.
Otherwise,
Acked-by: Chen-Yu Tsai <w...@csie.org>
> config PINCTRL_SUN8I_A23_R
> def_bool MACH_SUN8I
>
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