Hi,
On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
wrote:
> This adds support for RSB
> A83T RSB is compatible with A23 rsb.
>
> Signed-off-by: Vishnu Patekar
> ---
> arch/arm/boot/dts/sun8i-a83t.dtsi | 14 ++
> 1 file
On Sun, Jan 31, 2016 at 9:20 AM, Vishnu Patekar
wrote:
> APB1 is similar to sun4i-a10-apb0-clk, except different dividers.
>
> This adds support for apb1 on A83T.
>
> Signed-off-by: Vishnu Patekar
> ---
>
On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
wrote:
> Now that we have a driver for the R_PIO controller,
> add the corresponding device node to the dtsi.
>
> Signed-off-by: Vishnu Patekar
> ---
> arch/arm/boot/dts/sun8i-a83t.dtsi |
On Sun, Jan 31, 2016 at 9:20 AM, Vishnu Patekar
wrote:
> This adds A83T system bus clocks, bus gates, and clock resets.
>
> For ahb1 and ahb2, it's not clear which reset belongs to ahb1
> or ahb2; so named as ahb_reset0, ahb_reset1, ahb_reset2.
>
> Signed-off-by:
On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
<vishnupatekar0...@gmail.com> wrote:
> mmc clocks are compatible with that of earlier sun8i socs.
> This adds mmc0, mmc1, and mmc2 clock nodes for A83T.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0...@gmail.com>
A
On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
wrote:
> This adds A83T PRCM related clocks, clock resets.
>
> As a83t apb0 gates clock support is added earlier, this enables it.
> Apart from apb0 gates, other added clocks are compatible with
> earlier sun8i socs.
>
>
Hi,
On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
wrote:
> This enables mmc0.
>
> Signed-off-by: Vishnu Patekar
> Tested-by: LABBE Corentin
> ---
> .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts| 20
On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
wrote:
> This patch adds support for Sinovoip BPI-M3 A83T based board.
>
> It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI,
> mic, AP6212 Wifi, etc on it.
> It is paired with AXP813 PMIC which is almost
On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
wrote:
> A83T mmc is compatible with earliers sunxi socs.
> This adds mmc0, mmc1, and mmc2 controller nodes for A83T.
>
> Signed-off-by: Vishnu Patekar
> ---
>
On Mon, Feb 1, 2016 at 6:12 PM, Krzysztof Adamski wrote:
> H3 has additional PIO controller similar to what we can find on A23.
> It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.
>
> Signed-off-by: Krzysztof Adamski
> ---
>
On Tue, Feb 2, 2016 at 6:00 PM, Maxime Ripard
wrote:
> Hi Andre,
>
> On Mon, Feb 01, 2016 at 10:49:16PM +, André Przywara wrote:
>> On 01/02/16 18:27, Karsten Merker wrote:
>>
>> Hi Karsten,
>>
>> thank you very much for your feedback!
>>
>> > On Mon, Feb 01,
disable them.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun9i-a80-optimus.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts
b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index 7f6bf6138966..b447360d93e8 100644
---
This patch adds the basic and regulator bindings for the X-Powers AXP809
PMIC.
Also update the DC-DC converter operating frequency for AXP22X/AXP80X.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
Documentation/devicetree/bindings/mfd/axp20x.txt | 31 ++--
1 file c
-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/mfd/axp20x-rsb.c | 1 +
drivers/mfd/axp20x.c | 79 ++
include/linux/mfd/axp20x.h | 59 ++
3 files changed, 139 insertions(+)
diff --git a/drivers/mfd/axp20x-r
The AXP809 PMIC is the primary PMIC. It provides various supply voltages
for the SoC and other peripherals. The PMIC's interrupt line is
connected to NMI pin of the SoC.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun9i-a80-optimus.dts
el.com>
Cc: Jacob Pan <jacob.jun@linux.intel.com>
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f678c37107f5..7ea4e54f566a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11941
-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/regulator/axp20x-regulator.c | 14 +++---
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/drivers/regulator/axp20x-regulator.c
b/drivers/regulator/axp20x-regulator.c
index e86d1fc2d80b..f31d238e85e8 100644
--- a/d
a number of regulators
that have 2 linear ranges.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/regulator/axp20x-regulator.c | 32 +---
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/drivers/regulator/axp20x-regulator.c
b/drivers/reg
disable them.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
index 4d56dc69713c..98d9dc2d5259
-common-regulators.dtsi,
on the Cubieboard4. These aren't used in the board DTS anymore.
Regards
ChenYu
Chen-Yu Tsai (11):
MAINTAINERS: Add entry for X-Powers AXP family PMIC drivers
mfd: axp20x: Add bindings for AXP809 PMIC
mfd: axp20x: Add support for AXP809 PMIC
regulator: axp20x
on their
device node names.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/axp809.dtsi | 138 ++
1 file changed, 138 insertions(+)
create mode 100644 arch/arm/boot/dts/axp809.dtsi
diff --git a/arch/arm/boot/dts/axp809.dtsi b/arch/arm/boot/dts/
the "axp22x_" prefix from
DC1SW/DC5LDO supply handling code, as the AXP809 uses it as well.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/regulator/axp20x-regulator.c | 119 ++-
1 file changed, 90 insertions(+), 29 deletions(-)
diff
The AXP809 PMIC is the primary PMIC. It provides various supply voltages
for the SoC and other peripherals. The PMIC's interrupt line is connected
to NMI pin of the SoC.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
On Wed, Feb 3, 2016 at 12:21 AM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> Hi,
>
> On Tue, Feb 02, 2016 at 06:27:43PM +0800, Chen-Yu Tsai wrote:
>> These 3 regulators are provided in sunxi-common-regulators.dtsi.
>> 3.0V/3.3V and 5.0V are commonly used vo
On Wed, Feb 3, 2016 at 9:28 AM, Joe Perches <j...@perches.com> wrote:
> On Wed, 2016-02-03 at 11:19 +1100, Julian Calaby wrote:
>> On Tue, Feb 2, 2016 at 9:27 PM, Chen-Yu Tsai <w...@csie.org> wrote:
>> > Add an entry for X-Powers AXP family PMIC drivers and
Hi,
On Wed, Feb 3, 2016 at 5:21 AM, Krzysztof Adamski wrote:
> sunxi_pmx_set accepts pin number and then calculates offset by
> subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
> gets offset so we have to convert it to pin number so we won't get
> negative
On Wed, Feb 3, 2016 at 5:21 AM, Krzysztof Adamski wrote:
> This patch adds support for APB0 in H3. It seems to be compatible with
> earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
> etc).
>
> Signed-off-by: Krzysztof Adamski
> ---
>
Hi,
On Mon, Feb 1, 2016 at 10:26 PM, Hans de Goede wrote:
> Hi,
>
>
> On 01-02-16 07:37, Maxime Ripard wrote:
>>
>> Hi,
>>
>> On Fri, Jan 29, 2016 at 07:25:51AM +0100, Hans de Goede wrote:
>>>
>>> Hi,
>>>
>>> On 01/28/2016 08:29 PM, Maxime Ripard wrote:
On Thu, Jan
y: Vishnu Patekar <vishnupatekar0...@gmail.com>
>> ---
>> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>
> Acked-by: Rob Herring <r...@kernel.org>
>
>> drivers/clk/sunxi/clk-sunxi.c | 75
>> +++
>>
rtions(+)
>
> Acked-by: Rob Herring <r...@kernel.org>
Acked-by: Chen-Yu Tsai <w...@csie.org>
--
You received this message because you are subscribed to the Google Groups
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To unsubscribe from this group and stop receiving emails from it, send an emai
>>
>> until, this confusion is cleared keep it H3 way.
>>
>> Signed-off-by: Vishnu Patekar <vishnupatekar0...@gmail.com>
>> ---
>> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>> drivers/clk/sunxi/clk-sun8i-bus-gates.c | 2 ++
>> 2
On Sun, Feb 28, 2016 at 7:18 AM, Vishnu Patekar
wrote:
> This adds A83T system bus clocks, bus gates, and clock resets.
>
> Three ahb reset registers are combined into one node.
>
> Signed-off-by: Vishnu Patekar
> ---
>
Hi,
On Sun, Feb 28, 2016 at 7:18 AM, Vishnu Patekar
<vishnupatekar0...@gmail.com> wrote:
> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
> clock index 0b1x is PLL6.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0...@gmail.com>
> Acked-by:
Hi Lee,
On Mon, Feb 15, 2016 at 2:31 AM, Chen-Yu Tsai <w...@csie.org> wrote:
> Hi everyone,
>
> This is v2 of the AXP809 PMIC support series. This adds support for
> X-Powers' AXP809 PMIC. This is the primary PMIC accompanying Allwinner's
> A80 SoC. For now, only
On Thu, Jan 21, 2016 at 7:16 PM, Hans de Goede <hdego...@redhat.com> wrote:
> Hi,
>
> On 21-01-16 06:26, Chen-Yu Tsai wrote:
>>
>> According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
>> Switch to mmc3 for the onboard eMMC, and also assign vq
On Thu, Jan 21, 2016 at 8:25 PM, Hans de Goede <hdego...@redhat.com> wrote:
> Hi,
>
> On 21-01-16 13:23, Chen-Yu Tsai wrote:
>>
>> On Thu, Jan 21, 2016 at 7:16 PM, Hans de Goede <hdego...@redhat.com>
>> wrote:
>>>
>>> Hi,
>>>
&
de
support.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
index 382bd9fc5647..eb2ccd0a3bd5 100644
---
de
support.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun9i-a80-optimus.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts
b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index c0060e4f7379..958160e40fd0 100644
--- a/arch/ar
Let .set_ios() fail if mmc_regulator_set_ocr() fails to enable and set a
proper voltage for vmmc.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/mmc/host/sunxi-mmc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mm
de
support.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
index 13ce68f06dd6..bd2a3beb4629 10064
mode for A80 Optimus.
Patch 15 enables eMMC hardware reset and eMMC DDR52 mode for Cubieboard4.
Chen-Yu Tsai (15):
mmc: sunxi: Document host init sequence
mmc: sunxi: Return error on mmc_regulator_set_ocr() fail in .set_ios
op
mmc: sunxi: Block signal voltage switching (CMD11)
mmc
Now that clock delay settings for 8 bit DDR are correct, and vqmmc
support is available, we can enable MMC_CAP_1_8V_DDR support. This
enables MMC HS-DDR at up to 52 MHz, even if signal voltage switching
is not available.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/mmc/host
sun9i/A80 MMC controllers have a larger FIFO, and the FIFO DMA
trigger levels can be increased. Also, the mmc module clock parent
has a higher clock rate, and the sample and output delay phases
are different.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun9i-a80.dt
to say whether
adapting it's code to a modern mainline kernel would work. Block signal
voltage switching until someone has proper hardware to implement and
test this.
This only affects SD UHS-1 modes, as eMMC switches the voltage directly
without any signaling.
Signed-off-by: Chen-Yu Tsai &l
sunxi_mmc_init_host() originated from Allwinner kernel sources. The
magic numbers written to various registers was never documented.
Add comments for values found in Allwinner user manuals.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/mmc/host/sunxi-mmc.c | 12
mmc2_8bit_pins is used with eMMC chips, which also have a reset pin.
The MMC controller also has a reset output that is supported.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ar
bit and 8 bit are shared. The new values for the other SoCs were from
A83T user manual's "new timing mode" default values, which describes
them in clock phase, rather than delay periods. These values were used
without any modification. They may not be correct, but they work.
Signed-off-b
the hardware reset pin for emmc.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index b6ad7850fac6..1867af24ff52 100644
--- a/arch/ar
mmc2_8bit_pins is used with eMMC chips, which also have a reset pin.
The MMC controller also has a reset output that is supported.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun9i-a80.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/ar
Hi,
On Fri, Jan 22, 2016 at 9:23 AM, Siarhei Siamashka
wrote:
> On Thu, 21 Jan 2016 21:38:39 +0100
> Karsten Merker wrote:
>
>> Hello everybody,
>>
>> I have read today's IRC discussion about handling the regulator
>> control on the A64 via the
On Sat, Jan 23, 2016 at 4:44 AM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> On Thu, Jan 21, 2016 at 01:26:39PM +0800, Chen-Yu Tsai wrote:
>> sun9i/A80 MMC controllers have a larger FIFO, and the FIFO DMA
>> trigger levels can be increased. Also, the mmc modul
Hi,
On Sat, Jan 23, 2016 at 4:31 AM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> Hi,
>
> On Thu, Jan 21, 2016 at 01:26:35PM +0800, Chen-Yu Tsai wrote:
>> mmc2 and mmc3 are available on the same pins, with different mux values.
>> However, only mmc3 suppor
.
Also drop the space before function pointer arguments, since checkpatch
complains.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/clk/sunxi/clk-factors.c| 24 ++--
drivers/clk/sunxi/clk-factors.h| 13 ++-
drivers/clk/sunxi/clk-mod0.c | 20 ++--
drivers/clk/sunxi/clk
From: Maxime Ripard
The composite clock didn't have any unregistration function, which forced
us to use clk_unregister directly on it.
While it was already not great from an API point of view, it also meant
that we were leaking the clk_composite structure
callbacks.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/clk/sunxi/clk-factors.c | 30 --
drivers/clk/sunxi/clk-factors.h | 3 +++
2 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-fac
sunxi's factors clk did not have an unregister function. This means
multiple structs were leaked whenever a factors clk was unregistered.
Add an unregister function for it. Also keep pointers to the mux and
gate structs so they can be freed.
Signed-off-by: Chen-Yu Tsai <w...@csie.
is
useless.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/clk/sunxi/clk-sunxi.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 7e719d089017..5dd927859bc2 100644
--- a/drivers/clk/s
The factors clk implementation has been extended to support custom
recalc callbacks to support clocks that use one factor for certain
parents only, like a pre-divider.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/clk/sunxi/clk-sunxi.c
struct clk_factors_config contains shifts/widths for the factors of
the factors clk. This is used to read out the factors from the register
value. In no case is it written to, so make it const.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/clk/sunxi/clk-factors.c| 4 ++--
d
sun6i's AR100 clock is a classic factors clk case:
AR100 = ((parent mux) >> p) / (m + 1)
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/clk/sunxi/clk-sun6i-ar100.c | 235 ++--
1 file changed, 61 insertions(+), 174 deletions(-)
diff --git a
sun8i-a23-mbus-clk used sunxi's factors clk, which is nice for very
complicated clocks, but is not really needed here.
Convert sun8i-a23-mbus-clk to use clk_composite, as it is a gate + mux
+ divider. This makes the code easier to understand.
Signed-off-by: Chen-Yu Tsai <w...@csie.
sunxi_factors_register() does not check for failures or cleanup after
clk_register_composite() or other clk-related calls.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/clk/sunxi/clk-factors.c | 43 +++--
1 file changed, 28 insertions(
the reverse, i.e. rewriting a factors clk into
a composite clk, it is included because some changes overlap. I'm not
sure whether this approach is worthwhile, as it actually adds more code,
though it might make it easier to understand.
Regards
ChenYu
Chen-Yu Tsai (10):
clk: sunxi: factors: Make struct
The latest addition of H3 USB clocks placed them at the bottom. Move it
before A80 (sun9i), so they are sorted by SoC family then name.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/clk/sunxi/clk-usb.c | 24
1 file changed, 12 insertions(+), 12 del
On the A83T and H3, the SID block is at a different address.
Furthurmore, the e-fuses are at an offset of 0x200 within the
hardware's address space.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 7 +++
1 file changed, 7 insertions(+)
On Sat, Jan 23, 2016 at 4:39 AM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> Hi,
>
> On Thu, Jan 21, 2016 at 01:26:36PM +0800, Chen-Yu Tsai wrote:
>> According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
>> Switch to mmc3 for the onboard
On Sat, Feb 13, 2016 at 12:43 AM, Chen-Yu Tsai <w...@csie.org> wrote:
> On Sat, Feb 13, 2016 at 12:06 AM, Vishnu Patekar
> <vishnupatekar0...@gmail.com> wrote:
>> Hello Wens,
>>
>>
>> On Tue, Feb 2, 2016 at 2:44 PM, Chen-Yu Tsai <w...@csie.org> wr
The APB0 clock on A23 is a zero-based divider, not a power-of-two based
divider.
Note that this patch does not apply cleanly to kernels before 4.5-rc1,
which added CLK_OF_DECLARE support to this driver.
Fixes: 57a1fbf28424 ("clk: sunxi: Add A23 APB0 divider clock support")
Signed-off-b
disable them.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
index 8d8af1189d87..84a12fef5768
el.com>
Cc: Jacob Pan <jacob.jun@linux.intel.com>
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f678c37107f5..7
-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/mfd/axp20x-rsb.c | 1 +
drivers/mfd/axp20x.c | 79 ++
include/linux/mfd/axp20x.h | 59 ++
3 files changed, 139 insertions(+)
diff --git a/drivers/mfd/axp20x-r
The AXP809 PMIC is the primary PMIC. It provides various supply voltages
for the SoC and other peripherals. The PMIC's interrupt line is connected
to NMI pin of the SoC.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
the "axp22x_" prefix from
DC1SW/DC5LDO supply handling code, as the AXP809 uses it as well.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/regulator/axp20x-regulator.c | 119 ++-
1 file changed, 90 insertions(+), 29 deletions(-)
diff
on their
device node names.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/axp809.dtsi | 53 +++
1 file changed, 53 insertions(+)
create mode 100644 arch/arm/boot/dts/axp809.dtsi
diff --git a/arch/arm/boot/dts/axp809.dtsi b/arch/arm/boot/dts/
Originally the helper macros used uppercase regulator names, which
are primarily used to expand to the regulator ID enum, as the default
names. This is aestheticly unpleasent.
Since the of_match bits are the same, just lowercase, use that as the
default names instead.
Signed-off-by: Chen-Yu Tsai
On Mon, Feb 15, 2016 at 9:59 PM, Andre Przywara wrote:
> Hi Hans,
>
>
>
>>
>> p.s.
>>
>> I love the work you've been doing on the A64, I've not had a chance
>> to try it out yet though. Have you made any progress with getting
>> the mmc slot to work ? If not maybe I
On Mon, Feb 15, 2016 at 10:36 PM, Andre Przywara <andre.przyw...@arm.com> wrote:
> Hi Chen-Yu,
>
> On 15/02/16 14:23, Chen-Yu Tsai wrote:
>> On Mon, Feb 15, 2016 at 9:59 PM, Andre Przywara <andre.przyw...@arm.com>
>> wrote:
>>> Hi Hans,
>>>
&g
On Tue, Feb 16, 2016 at 4:04 AM, Mark Brown <broo...@kernel.org> wrote:
> On Mon, Feb 15, 2016 at 06:31:23PM +0800, Chen-Yu Tsai wrote:
>> The X-Powers AXP809 PMIC has a similar set of regulators as the AXP221,
>> though a few LDOs were removed, and a new switch output adde
On Tue, Feb 16, 2016 at 5:45 PM, Andre Przywara <andre.przyw...@arm.com> wrote:
> Hi Chen-Yu,
>
> On 13/02/16 02:44, Chen-Yu Tsai wrote:
>> Hi,
>>
>> On Fri, Feb 12, 2016 at 11:11 PM, Andre Przywara <andre.przyw...@arm.com>
>> wrote:
>>> We
On Thu, Feb 18, 2016 at 7:03 AM, Krzysztof Adamski
wrote:
> allwinner,sun8i-h3-apb0-gates-clk was added by
> commit ba83a11104ae ("pinctrl: sunxi: Add H3 R_PIO controller support")
> but the patch was missing proper binding documentation. This patch fixes
> this
Hi,
On Wed, Feb 17, 2016 at 3:43 AM, Andre Przywara wrote:
> Based on the Allwinner A64 user manual and on the previous sunxi
> pinctrl drivers this introduces the pin multiplex assignments for
> the ARMv8 Allwinner A64 SoC.
> Port A is apparently used for the fixed
On Sun, Feb 21, 2016 at 9:54 AM, hp197 wrote:
> After testing IRQ pins we found some bugs in the pinctrl declaration.
>
> Signed-off-by: hp197
Please resend with your full name on the commit and the SoB.
The patch itself looks good.
ChenYu
--
You
On Sun, Feb 21, 2016 at 3:17 PM, Henry Paulissen <draakje...@gmail.com> wrote:
> After testing IRQ pins we found some bugs in the pinctrl declaration.
>
> Signed-off-by: Henry Paulissen <he...@nitronetworks.nl>
Acked-by: Chen-Yu Tsai <w...@csie.org>
--
You receiv
Hi,
On Fri, Feb 12, 2016 at 5:31 PM, Chen-Yu Tsai <w...@csie.org> wrote:
> Hi everyone,
>
> This is v2 of the A80 APBS clock fixes series.
>
> When I did the A80 PRCM support, I failed to notice the A80's APBS clock
> was not the same as the A23's APB0 clock. The former i
Hi,
On Fri, Feb 12, 2016 at 11:11 PM, Andre Przywara wrote:
> We now catch and report a failing ioremap, also a failure in the final
> step of the clock registration is now handled and reported.
> Also warnings are turned into errors.
>
> Signed-off-by: Andre Przywara
On Sun, Feb 21, 2016 at 5:39 PM, Andre Przywara wrote:
> Currently we hard-code the base name for the PLL6 clock for both the
> sun4i and sun6i variants in the driver (pll6 and pll6x2, respectively).
> This unfortunately denies reusing this clock for the H3 and A64 PLL8
>
Hans de Goede <hdego...@redhat.com>
Fixes: 1b82b4e4f954 ("regulator: axp20x: Add support for AXP22X regulators")
then
Acked-by: Chen-Yu Tsai <w...@csie.org>
Also, this bug has been in since v4.2. Should we mark it for stable?
Regards
ChenYu
> ---
> drivers/regulator
AXP818 supports VBUS drive function, even though the manual does not
mention it.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
include/axp818.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/axp818.h b/include/axp818.h
index 003477f..5630eed
The FLDOs on AXP818 PMIC normally provide power to CPUS and USB HSIC PHY
on the A83T/H8.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
board/sunxi/board.c| 6 ++
drivers/power/Kconfig | 27 +++
drivers/power/axp818.
enables USB Kconfig options in Cubietruck_plus_defconfig.
Patch 15 ~ 17 is the minimal changes needed to enable USB on the
A83T boards I have. They are not the same as the kernel changes
I will submit, and should not be merged without discussion.
Regards
ChenYu
Chen-Yu Tsai (17):
power: axp818
The A83T has 3 USB PHYs: 1 for USB OTG, 1 for standard USB 1.1/2.0 host,
1 for USB HSIC.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/cpu/armv7/sunxi/usb_phy.c | 48 ++
include/configs/sun8i.h| 2 ++
2 files changed, 50 inse
We have a separate compatible for almost each SoC. Add one for the A83T.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/usb/host/ohci-sunxi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
index d4fb95a..6f3f4ce
The h8_homlet_v2 has 2 USB host ports, one connected to the OTG
controller, one connected to the EHCI/OHCI pair.
Also provide the card detect pin for MMC.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
configs/h8_homlet_v2_defconfig | 5 +
1 file changed, 5 insertions(+)
diff
axp818_init() is declared, but never defined.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
include/axp818.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/axp818.h b/include/axp818.h
index 46d05ad..c2f9847 100644
--- a/include/axp818.h
+++ b/include/axp818.h
@@ -53,8
This provides the minimal changes to the Cubietruck Plus dts to enable USB
in U-boot. It is not what will be submitted to the kernel.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/dts/sun8i-a83t-cubietruck-plus.dts | 12
1 file changed, 12 insertions(+)
diff --git
VBUS drive is supported on AXP221 and later PMICs. Rework the macros
so we can support this on later PMICs without too much work.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/gpio/axp_gpio.c | 25 ++---
include/axp221.h| 8
2 files chang
DLDO4 supplies power to the PD pins, and the AC200 Ethernet PHY /
composite video encoder.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
configs/h8_homlet_v2_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig
This provides the minimal changes to the H8Homlet v2 dts to enable USB
in U-boot. It is not what will be submitted to the kernel.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 12
1 file changed, 12 insertions(+)
diff
Like the Allwinner A33 SoC, the A83T is missing the config register
from the musb USB DRD hardware block. Use a known working value for
it.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/usb/musb-new/musb_regs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/d
This provides the minimal changes to the A83T dtsi to enable USB in
U-boot. It is not what will be submitted to the kernel.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/dts/sun8i-a83t.dtsi | 34 ++
1 file changed, 34 insertions(+)
diff --git
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