igned-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index 34b2a9249a94..095a5807d874 1
ither in software nor in the device tree binding.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 1dc4cfe81534..8089f36deeff 100644
--- a/arc
t, as mentioned above.
Patch 3 adds a device node for the PRCM.
Regards
ChenYu
Chen-Yu Tsai (3):
dt-bindings: clock: sunxi-ccu: Add compatible string for A83T PRCM
clk: sunxi-ng: a83t: Add support for A83T's PRCM
ARM: sun8i: a83t: Add device node for PRCM
.../devicetree/bindings/c
The A83T's PRCM has the same set of clocks and resets as the A64.
However, a few dividers are different. And due to the lack of a low
speed 32.768 kHz oscillator, a few of the clock parents are different.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun8i-r.c
On Sun, May 28, 2017 at 12:09 AM, Maxime Ripard
wrote:
> It appears that the total vertical resolution needs to be doubled when
> we're not in interlaced. Make sure that is the case.
>
> Signed-off-by: Maxime Ripard
Reviewed-by: Chen-Yu Tsai
--
You received this messag
On Mon, May 29, 2017 at 3:41 PM, Maxime Ripard
wrote:
> Hi,
>
> On Wed, May 24, 2017 at 08:13:20PM +0800, Icenowy Zheng wrote:
>> The 40-pin LCD connector on Lichee Pi Zero has backlight pins, which is
>> controlled by the PWM0 controller of the V3s SoC, and the controlling
>> part is on the board
y" in Chinese.
Finally, is there a preference for all lowercase defconfig file names?
Regards
ChenYu
> Cc: Icenowy Zheng
> Cc: Chen-Yu Tsai
> Cc: VishnuPatekar
> Signed-off-by: Jagan Teki
> ---
> board/sunxi/MAINTAINERS| 10
> ++
On Mon, May 29, 2017 at 11:37 PM, Jagan Teki wrote:
> On Mon, May 29, 2017 at 8:27 PM, Chen-Yu Tsai wrote:
>> On Mon, May 29, 2017 at 10:24 PM, Jagan Teki wrote:
>>> From: Jagan Teki
>>>
>>> - Rename Sinovoip BPI defconfigs to use small letter
>>>
Hi,
On Tue, May 30, 2017 at 5:58 AM, Karsten Merker wrote:
> On Tue, May 30, 2017 at 01:06:54AM +0530, Jagan Teki wrote:
>> From: Jagan Teki
>>
>> from BPI(BIPAI KEJI LIMITED) products the Bananapi board
>> is named as 'Bananapi M1' and this is the starting
>> bananapi board from M1 series.
>>
>
The PRCM takes PLL_PERIPH0 as one of its parents for the AR100 clock.
As such we need to be able to describe this relationship in the device
tree.
Export the PLL_PERIPH0 clock so we can reference it in the PRCM node.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.h
ither in software nor in the device tree binding.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 1dc4cfe81534..49aeb56970ba 100644
--- a
The AR100 clock within the R_CCU (PRCM) has the PLL_PERIPH0 as one of
its parents.
This adds the reference in the device tree describing this relationship.
This patch uses a raw number for the clock index to ease merging by
avoiding cross tree dependencies.
Signed-off-by: Chen-Yu Tsai
---
arch
The AR100 clock in the PRCM has parents, one of which is pll-periph from
the main CCU.
Add it to the list of required clocks for the PRCM CCU.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 7 ---
1 file changed, 4 insertions(+), 3 deletions
The AR100 clock within the R_CCU (PRCM) has the PLL_PERIPH0 as one of
its parents.
This adds the reference in the device tree describing this relationship.
This patch uses a raw number for the clock index to ease merging by
avoiding cross tree dependencies.
Signed-off-by: Chen-Yu Tsai
---
arch
The PRCM takes PLL_PERIPH0 as one of its parents for the AR100 clock.
As such we need to be able to describe this relationship in the device
tree.
Export the PLL_PERIPH0 clock so we can reference it in the PRCM node.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 4
from other sun8i implementations include different clock parent
names, due to the A83T not having a proper 32.768 kHz oscillator, and
different predividers for the IR clock.
Still to come are support for R_PIO and RSB on the A83T.
Regards
ChenYu
Chen-Yu Tsai (6):
dt-bindings: clock: sunxi-ccu
The HDMI controller in the A31 SoC is slightly different from the
earlier version. In addition to the TMDS clock and DDC controls,
this version now takes a second DDC clock input.
Add a compatible string for it, and add the DDC clock input to the
list of clocks required.
Signed-off-by: Chen-Yu
On the A31, the HDMI TMDS clock has a different value offset for the
divider.
This patch adds support for custom offsets to the TMDS clock.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c | 26 +++---
1 file changed, 19 insertions(+), 7 deletions
. Then we can just pass
mode_config.num_crtc in.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index f19100c91c2b..ed75a779ae4b
te straightforward.
I also had simultaneous output on both display pipelines on the SinA31s,
one with an LCD panel and the other using HDMI. After boot, both screens
showed a proper console. The HDMI screen had higher resolution, so the
console was limited to the upper left corner.
Regards
The MSI Primo81 tablet has a micro HDMI connector at the bottom.
This is connected to the SoCs HDMI output.
Enable the display pipeline and the HDMI output.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun6i-a31s-primo81.dts | 25 +
1 file changed, 25 insertions
The DDC parent clock on the A31 SoC is also conveniently named
"hdmi-ddc", which results in a name collision when the hdmi driver
registers its internal DDC divider clock.
Rename the internal clock to "hdmi-ddc-divider".
Signed-off-by: Chen-Yu Tsai
---
d
unbind function.
Also rename the err_cleanup_connector label to err_cleanup_encoder,
since it is the encoder that gets cleaned up.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 25 +
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a
different offset.
This patch adds support for different variants of the DDC clock.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c | 42 --
1 file changed, 34 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
b
The A31 Humminbird has an HDMI connector wired to the HDMI pins
on the SoC. Enable HDMI support for this board.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31
The A31's HDMI controller's TMDS clock is slightly different.
There is an offset of 1 between the divider value and the actual
value programmed into the registers.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_hdmi.h | 1 +
drivers/gpu/drm/sun4i/sun4i_hdmi_tmds
On systems with 2 TCONs such as the A31, it is possible to demux the
output of the TCONs to one encoder.
Add support for this for the A31.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 61 ++
1 file changed, 61 insertions(+)
diff
s its parent.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c | 51 -
1 file changed, 28 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
index 5cf2527
The DDC block for the HDMI controller is different on the A31.
This patch adds the register definitions.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_hdmi.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
b
encoders added in the second pass will be the last entries in the
list.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 24
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i
The Sinlinx SinA31s has an HDMI connector wired to the HDMI pins
from the SoC.
Enable the display pipeline and the HDMI output.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot
Now that we support the HDMI controller on the A31 SoC, we can add it
to the device tree.
This adds a device node for the HDMI controller, and the of_graph nodes
connecting it to the 2 TCONs.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun6i-a31.dtsi | 55
- Separate DDC parent clock
This patch adds support for it.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_hdmi.h | 3 +
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 141 +
2 files changed, 144 insertions(+)
diff --git a/drivers/gpu/drm/sun4i
different offset.
This patch adds support for this variant.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_hdmi.h | 1 +
drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
b/drivers/gpu
The 2x outputs of the 2 video PLL clocks are directly used by the
HDMI controller block.
Export them so they can be referenced in the device tree.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun6i-a31.h | 8 ++--
include/dt-bindings/clock/sun6i-a31-ccu.h | 4
2 files
pointers to the
above functions, structures, and the different initial values.
Another flag notates whether there is a separate DDC parent clock.
If not, the TMDS clock is passed to the DDC clock create function,
as before.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 2
On Sat, Jun 3, 2017 at 3:30 AM, Maxime Ripard
wrote:
> On Fri, Jun 02, 2017 at 06:10:15PM +0800, Chen-Yu Tsai wrote:
>> The DDC parent clock on the A31 SoC is also conveniently named
>> "hdmi-ddc", which results in a name collision when the hdmi driver
>> registers
The A83T has 1 pingroup with 13 pins belonging to the R_PIO
or special pin controller.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
The R_PIO on the A83T is almost the same as the one found on the A64,
except that the CIR_RX function was moved from pin PL11 to pin PL12.
Add a driver for it.
Signed-off-by: Chen-Yu Tsai
---
drivers/pinctrl/sunxi/Kconfig| 4 +
drivers/pinctrl/sunxi/Makefile
pinctrl driver.
Patch 3 adds a device node for the pin controller.
Please have a look.
Regards
ChenYu
Chen-Yu Tsai (3):
dt-bindings: pinctrl: sunxi: Add compatible string for A83T R_PIO
pinctrl: sunxi: Add support for A83T R_PIO
ARM: sun8i: a83t: Add device node for R_PIO
.../bindings
The R_PIO on the A83T is almost the same as the one found on the A64,
except that the CIR_RX function was moved from pin PL11 to pin PL12.
Add a compatible string for it.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
1 file changed
On Sat, Jun 3, 2017 at 3:38 AM, Maxime Ripard
wrote:
> On Fri, Jun 02, 2017 at 06:10:18PM +0800, Chen-Yu Tsai wrote:
>> The HDMI controller found in earlier Allwinner SoCs have slight
>> differences:
>>
>> - Need different initial values for the PLL related re
On Sat, Jun 3, 2017 at 3:41 AM, Maxime Ripard
wrote:
> On Fri, Jun 02, 2017 at 06:10:19PM +0800, Chen-Yu Tsai wrote:
>> The HDMI controller found in the A31 SoCs is slightly different
>> from the one already supported, which is found in the A10s:
>>
>> - Need diffe
On Sat, Jun 3, 2017 at 3:42 AM, Maxime Ripard
wrote:
> On Fri, Jun 02, 2017 at 06:10:24PM +0800, Chen-Yu Tsai wrote:
>> The MSI Primo81 tablet has a micro HDMI connector at the bottom.
>> This is connected to the SoCs HDMI output.
>>
>> Enable the display p
-by: Chen-Yu Tsai
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 35 ++-
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 166c9ef884dc..373df5ee1c23
Now that the R_CCU device tree binding headers have been merged, we
can convert the raw number references in the device trees to use the
defined macros.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a
branch. Once these are merged,
I think it's time to send off pull requests for our fixes branches.
ChenYu
Chen-Yu Tsai (2):
ARM: sunxi: h3-h5: Convert R_CCU raw numbers to macros
arm64: allwinner: a64: Convert CCU raw number references to macros
arch/arm/boot/dts/sunxi-h3-h5
Hi Marc,
On Mon, May 22, 2017 at 10:25 PM, Chen-Yu Tsai wrote:
> On Mon, May 22, 2017 at 5:41 PM, Icenowy Zheng wrote:
>>
>>
>> 于 2017年5月22日 GMT+08:00 下午5:39:22, Marc Zyngier 写到:
>>>On 18/05/17 08:16, Icenowy Zheng wrote:
>>>> Add support for the newly
On Mon, Jun 5, 2017 at 4:14 PM, Maxime Ripard
wrote:
> On Mon, Jun 05, 2017 at 12:32:22PM +0800, Chen-Yu Tsai wrote:
>> Hi Maxime,
>>
>> These are some clean up patches for 4.12. They convert raw number
>> references for the CCU and R_CCU nodes, from when the CCU/R_C
Now that the R_CCU device tree binding headers have been merged, we
can convert the raw number references in the device trees to use the
defined macros.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a
-by: Chen-Yu Tsai
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 35 ++-
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 166c9ef884dc..23a531c80308
equests for our fixes branches.
ChenYu
Chen-Yu Tsai (2):
ARM: sunxi: h3-h5: Convert R_CCU raw numbers to macros
arm64: allwinner: a64: Convert CCU raw number references to macros
arch/arm/boot/dts/sunxi-h3-h5.dtsi| 8 +++---
arch/arm64/boot/dts/allwinner/sun50
mon quirk configured in the config struct.
>
> Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
--
You received this message because you are subscribed to the Google Groups
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gt; ranges;
>
> + syscon: syscon@1c0 {
> + compatible = "syscon",
> + "allwinner,sun8i-a83t-system-controller";
syscon is the most generic compatible string here.
It should be the last o
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + mdio: mdio {
> + #address-cells = <1>;
> +
and tied
> into this codec driver with the audio card's aux_dev.
>
> In addition, the V3s does not have LINEIN, LINEOUT, MBIAS and MIC2,
> MIC3, and the FIFO related registers are like H3.
>
> Signed-off-by: Icenowy Zheng
> Acked-by: Rob Herring
Reviewed-by: Chen-Yu Tsai
pecial set, and use it when the SoC has no MIC2 and Line In.
>
> Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
--
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To unsubscribe from this group and stop receiving emails f
On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
> From: "tpear...@raptorengineering.com"
You should fix his name here.
>
> This patch enables non-secure access to all system peripherals
> controlled by the STMA, and additionally sets the secure RAM
> range to 64k in line with other sunxi d
On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
> A83T has some secure SRAM that can be used to place the PSCI code.
>
> Add the configuration of them.
>
> Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
--
You received this message because you are subscribed to th
,7 +84,7 @@ int print_cpuinfo(void)
> #elif defined CONFIG_MACH_SUN8I_A33
> printf("CPU: Allwinner A33 (SUN8I %04x)\n", sunxi_get_sram_id());
> #elif defined CONFIG_MACH_SUN8I_A83T
> - printf("CPU: Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id());
> + p
On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
> As we have now a basical implementation of PSCI for A83T, enable
> non-secure boot support and PSCI on A83T now.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm/mach-sunxi/Kconfig | 4
> 1 file changed, 4 insertions(+)
>
> diff --git
u32 vdd_pwr_reset; /* 0x120 */
> u8 res10[0x1c]; /* 0x124 */
> - u32 cpu_pwr_clamp[4]; /* 0x140 but first one is actually unused */
> - u8 res11[0x30]; /* 0x150 */
> + u32 cpu_pwr_clamp[2][4];/* 0x140 but first one is actually
On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
> From: Chen-Yu Tsai
>
> The A80/A83T SoCs has a different CPUCFG register layout, likely due to
> having 2 clusters. The A83T SoC has also a small extra CPUCFG part
> located at single cluster SoCs' CPUCFG address (in CPU
On Wed, Jun 7, 2017 at 11:40 AM, Icenowy Zheng wrote:
>
>
> 于 2017年6月7日 GMT+08:00 上午11:36:27, Chen-Yu Tsai 写到:
>>On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
>>> As we have now a basical implementation of PSCI for A83T, enable
>>> non-secure
On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
> A83T SoC has two part of CPUCFG configurations -- one part is at
> 0x0170, which contains most of the controls, and is like the one in
> A80; the another part is at 0x01f01c00 (like other post-sun6i SoCs), but
> contains now only a few reg
On Wed, Jun 7, 2017 at 11:48 AM, Chen-Yu Tsai wrote:
> On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
>> A83T SoC has two part of CPUCFG configurations -- one part is at
>> 0x0170, which contains most of the controls, and is like the one in
>> A80; the another
On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
> From: Chen-Yu Tsai
>
> Allwinner A80 and A83T SoCs have two clusters of CPU, each cluster
> contains 4 cores. A80 is Cortex-A15 + Cortex-A7 configuration, while
> A83T has two clusters of Cortex-A7.
>
> This patch adds
On Wed, Jun 7, 2017 at 2:50 PM, Maxime Ripard
wrote:
> On Wed, Jun 07, 2017 at 11:47:24AM +0800, Chen-Yu Tsai wrote:
>> On Wed, Jun 7, 2017 at 11:40 AM, Icenowy Zheng wrote:
>> >
>> >
>> > 于 2017年6月7日 GMT+08:00 上午11:36:27, Chen-Yu Tsai 写到:
>> >&
On Wed, Jun 7, 2017 at 2:58 PM, Icenowy Zheng wrote:
>
>
> 于 2017年6月7日 GMT+08:00 下午2:44:21, Maxime Ripard
> 写到:
>>On Wed, Jun 07, 2017 at 08:47:18AM +0800, Icenowy Zheng wrote:
>>> diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
>>b/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
>>>
On Mon, Jun 5, 2017 at 9:51 PM, Maxime Ripard
wrote:
> On Sat, Jun 03, 2017 at 10:44:24PM +0800, Chen-Yu Tsai wrote:
>> Hi,
>>
>> This series adds support for the R_PIO pin controller on the A83T.
>> The pins managed this controller are mainly used for communicating
The MSI Primo81 tablet has a 3500 mAh 3.7V LiPo battery.
Enable the PMIC's battery power supply so the battery can be monitored.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun6i-a31s-primo81.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31s-pr
".
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun6i-a31s-primo81.dts | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts
b/arch/arm/boot/dts/sun6i-a31s-primo81.dts
index f3712753fa42..73b163a7d9dd 100644
---
On Thu, Jun 8, 2017 at 6:47 AM, Ilia Mirkin wrote:
> On Wed, Jun 7, 2017 at 6:36 PM, Rob Herring wrote:
>> On Fri, Jun 02, 2017 at 09:42:19PM +0200, Maxime Ripard wrote:
>>> On Fri, Jun 02, 2017 at 06:10:24PM +0800, Chen-Yu Tsai wrote:
>>> > The MSI Primo81 tablet
On Mon, Jun 12, 2017 at 10:12 AM, Jonathan Liu wrote:
> The drm_get_edid function should be used instead of drm_do_get_edid by
> exposing the DDC bus as an I2C adapter. Implement this for A10s.
Nice!
>
> Signed-off-by: Jonathan Liu
> ---
> drivers/gpu/drm/sun4i/Makefile | 1 +
> driv
On Tue, Jun 13, 2017 at 5:43 PM, Maxime Ripard
wrote:
> On Sat, Jun 10, 2017 at 10:57:28PM +0800, icen...@aosc.io wrote:
>> 在 2017-06-09 22:46，Maxime Ripard 写道：
>> > On Thu, Jun 08, 2017 at 01:01:53PM +0800, icen...@aosc.io wrote:
>> > > 在 2017-06-07 22:38，Maxime Ripard 写道：
>> > > > On Wed, Jun 07
gards
ChenYu
Chen-Yu Tsai (6):
dt-bindings: mfd: axp20x: Add AXP806 to supported list of chips
dt-bindings: mfd: axp20x: Introduce bindings for AXP813
mfd: axp20x: Add support for AXP813 PMIC
ARM: sun8i: a83t: Add device node and pinmux setting for RSB
controller
ARM: sun8i: a83t: Add d
The AXP813/AXP818 PMICs used with the A83T/H8 SoCs are actually 2 dies
in one package sharing the serial bus (I2C/RSB) pins. One die is the
actual PMIC. The other is an AC100 codec / RTC combo chip.
This patch adds a device node for the PMIC die.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot
power button
enabled.
Signed-off-by: Chen-Yu Tsai
---
drivers/mfd/axp20x-rsb.c | 1 +
drivers/mfd/axp20x.c | 22 ++
include/linux/mfd/axp20x.h | 29 +
3 files changed, 52 insertions(+)
diff --git a/drivers/mfd/axp20x-rsb.c b/drivers/mfd/a
d-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/mfd/axp20x.txt | 49 +---
1 file changed, 44 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt
b/Documentation/devicetree/bindings/mfd/axp20x.txt
index 211a100c6b20..1dff7e2
The binding already lists compatibles and regulators for the AXP806,
but it is missing from the list of supported chips at the beginning.
Add it.
Fixes: 204ae2963e10 ("mfd: axp20x: Add bindings for AXP806 PMIC")
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/mfd/
.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
index 027602ce03d1..933245758603 100644
The A83T has an RSB controller for talking to the PMIC and audio codec.
Add a device node for it. Since there is only one usable pinmux setting,
for it, add that as well.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 22 ++
1 file changed, 22 insertions
On Mon, Jun 5, 2017 at 10:00 PM, Maxime Ripard
wrote:
> On Sat, Jun 03, 2017 at 10:33:25PM +0800, Chen-Yu Tsai wrote:
>> On Sat, Jun 3, 2017 at 3:30 AM, Maxime Ripard
>> wrote:
>> > On Fri, Jun 02, 2017 at 06:10:15PM +0800, Chen-Yu Tsai wrote:
>> >> The DDC
t; > >
>>> > >
>>> > > 于 2017年6月7日 GMT+08:00 下午8:11:12, Marc Zyngier
>>> > > 写到:
>>> > > > On 07/06/17 08:00, Chen-Yu Tsai wrote:
>>> > > > > On Wed, Jun 7, 2017 at 2:50 PM, Maxime Ripard
>>> &
On Sat, Jun 24, 2017 at 2:24 PM, Danny Milosavljevic
wrote:
> Since it's now possible to have a DAPM mixer control with multiple channels,
> use it to cut down the total number of controls.
>
> Signed-off-by: Danny Milosavljevic
> ---
> sound/soc/sunxi/sun4i-codec.c | 27
On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe
wrote:
> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote:
>> On 31/05/17 08:18, Corentin Labbe wrote:
>> > The dwmac-sun8i is a heavy hacked version of stmmac hardware by
>> > allwinner.
>> > In fact the only common part is the descrip
On Tue, Jun 27, 2017 at 5:41 PM, Maxime Ripard
wrote:
> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote:
>> Hi,
>>
>> (CC:ing some people from that Rockchip dmwac series)
>>
>> On 27/06/17 09:21, Corentin Labbe wrote:
>> > On Tue, Jun
On Tue, Jun 27, 2017 at 6:17 PM, Icenowy Zheng wrote:
>
>
> 于 2017年6月27日 GMT+08:00 下午6:11:47, Chen-Yu Tsai 写到:
>>On Tue, Jun 27, 2017 at 5:41 PM, Maxime Ripard
>> wrote:
>>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote:
>>>> Hi,
>&g
gt;>> On 27/06/17 09:21, Corentin Labbe wrote:
>>>> On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote:
>>>>> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe
>>>>> wrote:
>>>>>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, A
On Wed, Jun 28, 2017 at 4:25 PM, Danny Milosavljevic
wrote:
> Hi,
>
>> > > -static const struct snd_kcontrol_new sun4i_codec_left_mixer_controls[]
>> > > = {
>> > > - SOC_DAPM_SINGLE("Left DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
>> > > - SUN4I_CODEC_DAC_ACTL_LDACLM
Hi,
On Sat, Jun 24, 2017 at 2:24 PM, Danny Milosavljevic
wrote:
> This patchset adds some mixer controls to sun4i-codec for the Allwinner A10
> and the Allwinner A20.
>
> It also adds a mux for the capture source and the PGA for the MIC2 preamp.
>
> Where possible, it uses SOC_DAPM_DOUBLE in orde
Hi,
On Wed, Jun 28, 2017 at 6:52 PM, Jonathan Liu wrote:
> The documentation for drm_do_get_edid in drivers/gpu/drm/drm_edid.c states:
> "As in the general case the DDC bus is accessible by the kernel at the I2C
> level, drivers must make all reasonable efforts to expose it as an I2C
> adapter an
On Fri, Jun 30, 2017 at 6:22 AM, Jonathan Liu wrote:
> Hi Maxime,
>
> On 30 June 2017 at 01:56, Maxime Ripard
> wrote:
>> On Wed, Jun 28, 2017 at 08:39:33PM +1000, Jonathan Liu wrote:
>>> >> + u32 int_status;
>>> >> + u32 fifo_status;
>>> >> + /* Read needs empty flag unset, write nee
On Fri, Jun 30, 2017 at 5:19 AM, Rob Herring wrote:
> On Tue, Jun 27, 2017 at 07:07:34PM +0800, Yong Deng wrote:
>> Add binding documentation for Allwinner CSI.
>
> For the subject:
>
> dt-bindings: media: Add Allwinner Camera Sensor Interface (CSI)
>
> "binding documentation" is redundant.
>
>>
>
On Wed, Jul 5, 2017 at 4:04 AM, Priit Laes wrote:
> SATA clock on sun4i/sun7i is of type (parent) / M / 6 where
> 6 is fixed post-divider.
>
> Signed-off-by: Priit Laes
Reviewed-by: Chen-Yu Tsai
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On Wed, Jul 5, 2017 at 4:04 AM, Priit Laes wrote:
> Allwinner A20 is now driven by sunxi-ng CCU driver.
>
> Add devicetree binding for it.
>
> Acked-by: Rob Herring
> Signed-off-by: Priit Laes
Reviewed-by: Chen-Yu Tsai
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On Wed, Jul 5, 2017 at 4:04 AM, Priit Laes wrote:
> Allwinner A10 is now driven by sunxi-ng CCU driver.
>
> Add devicetree binding for it.
>
> Acked-by: Rob Herring
> Signed-off-by: Priit Laes
Reviewed-by: Chen-Yu Tsai
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On Thu, Jul 6, 2017 at 1:49 AM, Code Kipper wrote:
> On 5 July 2017 at 18:20, Maxime Ripard
> wrote:
>> On Wed, Jul 05, 2017 at 05:43:24PM +0200, codekip...@gmail.com wrote:
>>> From: Marcus Cooper
>>>
>>> There are a lot of changes to the sun8i-h3 i2s block but not enough
>>> to warrant to a n
Hi Corentin,
On Thu, Jul 6, 2017 at 5:45 PM, David Miller wrote:
> From: Corentin Labbe
> Date: Thu, 6 Jul 2017 10:51:47 +0200
>
>> On Sun, Jul 02, 2017 at 02:31:59PM +0200, Corentin Labbe wrote:
>>> Since internal phy-mode is reserved for non-xMII protocol we cannot use
>>> it with dwmac-sun8i
than Liu
This should have
Fixes: 9026e0d122ac ("drm: Add Allwinner A10 Display Engine support")
Otherwise,
Reviewed-by: Chen-Yu Tsai
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